专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160224480A1 SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF 审中-公开
标题翻译：半导体存储器和数据输入/输出方法
公开(公告)号：US20160224480A1
公开(公告)日：2016-08-04
申请号：US14713738
申请日：2015-05-15
申请人： SK hynix Inc.
发明人： Kie Bong KU
IPC分类号： G06F13/16 , G06F13/42 , G06F9/445
CPC分类号： G06F13/1668 , G06F13/4204 , G06F13/4282
摘要： A semiconductor memory apparatus may include a write data bus inversion unit and a write data polarity change unit. The write data bus inversion unit may invert a level of an input data and may generate an inversion change data when a majority of the input data have a predetermined level. The write data polarity change unit may invert a level of the inversion change data based on a write signal and a first bank address signal and generate a polarity change data.
摘要翻译：半导体存储装置可以包括写数据总线反转单元和写数据极性改变单元。写数据总线反转单元可以反转输入数据的电平，并且当大多数输入数据具有预定电平时可产生反转改变数据。写数据极性改变单元可以基于写信号和第一存储体地址信号反转反转变化数据的电平，并产生极性变化数据。

2. 发明授权

US08959256B2 Peripheral equipment and parallel bus system 有权
标题翻译：外围设备和并行总线系统
公开(公告)号：US08959256B2
公开(公告)日：2015-02-17
申请号：US13813109
申请日：2010-11-11
申请人： Toshiyuki Yamashita , Yuji Hiraoka
发明人： Toshiyuki Yamashita , Yuji Hiraoka
IPC分类号： G06F3/00 , G06F5/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4204 , G06F13/14
摘要： Bus lines 20, 21 are connected to peripheral devices 1, 2 such that the polarities of the bus lines are replaced with each other according to an attachment position, and information acquisition units 16-1, 16-2 determine an attachment position P1 if the polarities of a connector terminal 10-1 (or 10-2) and a connector terminal 11-1 (or 11-2) are plus and minus, and determines an attachment position P2 if minus and plus.
摘要翻译：总线20,21与外围装置1,2连接，使得总线的极性根据安装位置相互替换，信息获取单元16-1,16-2确定附接位置P1，如果连接器端子10-1（或10-2）和连接器端子11-1（或11-2）的极性为正负，并且如果为负，则确定附接位置P2。

3. 发明申请

US20120119854A1 SEGMENTED TRANSMISSION SIGNAL CIRCUIT 审中-公开
标题翻译：分段传输信号电路
公开(公告)号：US20120119854A1
公开(公告)日：2012-05-17
申请号：US13196572
申请日：2011-08-02
申请人： Chih-Chuan Huang
发明人： Chih-Chuan Huang
IPC分类号： H01P3/08 , H01P1/10
CPC分类号： G06F13/4068 , G06F13/4004 , G06F13/4204
摘要： A segmented transmission signal circuit is provided with a parallel bus of data transmission. The bus includes a plurality of sections, each section transmits a corresponding parallel data of multiple bits, and the parallel data corresponding to different sections are in different bit orders.
摘要翻译：分段传输信号电路具有数据传输的并行总线。总线包括多个部分，每个部分发送相应的多个比特的并行数据，并且对应于不同部分的并行数据具有不同的比特顺序。

4. 发明授权

US06993619B2 Single request data transfer regardless of size and alignment 失效
公开(公告)号：US06993619B2
公开(公告)日：2006-01-31
申请号：US10249302
申请日：2003-03-28
申请人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
发明人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
IPC分类号： G06F13/40 , H04L12/56
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

5. 发明授权

US06721918B2 Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect 有权
标题翻译：用于编码总线以最小化同时切换输出效果的方法和装置
公开(公告)号：US06721918B2
公开(公告)日：2004-04-13
申请号：US09750297
申请日：2000-12-29
申请人： Keith Self , John Urbanski
发明人： Keith Self , John Urbanski
IPC分类号： H03M1300
CPC分类号： G06F13/4204 , G06F13/4068
摘要： A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.
摘要翻译：总线具有第一组数据线和第二组数据线。在一个实施例中，总线具有选择器电路，用于对第一组数据线中的数据线的数量和具有一定值的第二组数据线进行计数，并且基于计数来选择要反转的一组数据线。在一个实施例中，总线具有第一反相器，用于反转所选择的数据线组和第二反相器，以基于添加的控制线的值重新反转在接收机处选择的数据线组。

6. 发明申请

US20020087936A1 Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect 有权
标题翻译：用于编码总线以最小化同时切换输出效果的方法和装置
公开(公告)号：US20020087936A1
公开(公告)日：2002-07-04
申请号：US09750297
申请日：2000-12-29
发明人： Keith Self , John Urbanski
IPC分类号： H03M013/09
CPC分类号： G06F13/4204 , G06F13/4068
摘要： A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.
摘要翻译：总线具有第一组数据线和第二组数据线。在一个实施例中，总线具有选择器电路，用于对第一组数据线中的数据线的数量和具有一定值的第二组数据线进行计数，并且基于计数来选择要反转的一组数据线。在一个实施例中，总线具有第一反相器，用于反转所选择的数据线组和第二反相器，以基于添加的控制线的值重新反转在接收机处选择的数据线组。

7. 发明授权

US4463421A Serial/parallel input/output bus for microprocessor system 失效
标题翻译：用于微处理器系统的串行/并行输入/输出总线
公开(公告)号：US4463421A
公开(公告)日：1984-07-31
申请号：US517383
申请日：1983-07-26
申请人： Gerald E. Laws
发明人： Gerald E. Laws
IPC分类号： G06F13/38 , G06F13/42 , G06F15/78 , G06F3/00 , G06F13/00
CPC分类号： G06F15/786 , G06F13/38 , G06F13/4204
摘要： A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. For a given set of addresses parallel data transfers occur and for a different set of addresses serial data transfers occur. A single instruction may transfer one bit, multiple bits in series, or bytes or words in parallel; the serial or parallel mode is specified by the address, so software may be written without regard for the type of interface. This serial/parallel I/O port shares the address/data bus with memory and may be used with any memory-mapped peripheral.
摘要翻译： MOS / LSI型单片微处理器器件包含一个ALU，多个内部总线，多个地址/数据寄存器，以及一个带相关控制解码或微控制器电路的指令寄存器。该设备通过双向复用的地址/数据总线和多个控制线与外部存储器和外设进行通信。对于给定的地址集合，并行数据传输发生，并且对于不同的地址集合，串行数据传输发生。单个指令可以并行传输一个位，多个位，或者字节或字节; 串行或并行模式由地址指定，因此软件可能不考虑接口类型。该串行/并行I / O端口与存储器共享地址/数据总线，并可与任何内存映射外设一起使用。

8. 发明申请

US20170139869A1 AVIONICS SYSTEM, ARCHITECTURE, AND METHOD 审中-公开
公开(公告)号：US20170139869A1
公开(公告)日：2017-05-18
申请号：US15351412
申请日：2016-11-14
申请人： Sandel Avionics, Inc.
发明人： Gerald J. Block , Delmar M. Fadden , John Morton, III
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4068 , G06F11/1004 , G06F13/4204 , G08G5/025
摘要： Systems and methods according to present principles provide a test architecture which is designed to support software and hardware testing in an automated environment. Systems and methods are described which include a functional definition and architecture of the test system including the host environment, host-user interface, test scripts, host-to-target communications, target test module, target test shell, target commands and other supporting aspects.

9. 发明申请

US20170052519A1 FORMING A LOGICAL MICROCONTROLLER FROM AT LEAST TWO PHYSICAL MICROCONTROLLERS ON A COMMON SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：在通用半导体基板上形成来自最少两个物理微控制器的逻辑微控制器
公开(公告)号：US20170052519A1
公开(公告)日：2017-02-23
申请号：US15306937
申请日：2015-02-24
申请人： Robert Bosch GmbH
发明人： Axel Aue , Hans-Walter Schmitt
IPC分类号： G05B19/042 , G06F13/42 , G06F13/40
CPC分类号： G05B19/0421 , G05B2219/2224 , G05B2219/45018 , G06F13/4068 , G06F13/4204 , G06F13/4282
摘要： A system of at least two microcontrollers on a common semiconductor substrate, each of the at least two microcontrollers respectively having one hardware interface, and the at least two microcontrollers being coupled in data-transmitting fashion via the hardware interfaces by a coupling device.
摘要翻译：一种在公共半导体衬底上的至少两个微控制器的系统，所述至少两个微控制器中的每一个分别具有一个硬件接口，并且所述至少两个微控制器通过耦合器件经由所述硬件接口以数据传输方式耦合。

10. 发明授权

US09379791B2 Multiple input multiple output (MIMO) communication systems and methods for chip to chip and intrachip communication 有权
标题翻译：多输入多输出（MIMO）通信系统和芯片到芯片和内部通信的方法
公开(公告)号：US09379791B2
公开(公告)日：2016-06-28
申请号：US14490818
申请日：2014-09-19
申请人： QUALCOMM Incorporated
发明人： RaviKiran Gopalan , Danlu Zhang
IPC分类号： H04B7/02 , H04B7/04 , H04B7/06 , H04B15/00 , G06F13/42 , H04B7/00
CPC分类号： H04B7/0413 , G06F13/4204 , G06F2213/0038 , H04B7/00 , H04B7/0626 , H04B15/00
摘要： Multiple input multiple output (MIMO) communication systems and methods for chip to chip and intrachip communication are disclosed. In one aspect, MIMO techniques that have been applied to wireless communication systems are applied to interchip and intrachip communication systems. In particular, a transfer function is applied at the transmitter, and a reverse transfer function is applied at the receiver. The transfer function dynamically changes based on channel conditions to cancel or otherwise mitigate electromagnetic interference (EMI) and crosstalk conditions. In an exemplary aspect, a sum of power levels across the channels may have a maximum. To abide by such power level constraint, the transfer function may be optimized to reduce interference while remaining within the power level constraint.
摘要翻译：公开了用于芯片到芯片和内部通信的多输入多输出（MIMO）通信系统和方法。在一个方面，已经应用于无线通信系统的MIMO技术被应用于芯片间和内部通信系统。特别地，在发射机处应用传递函数，并且在接收机处应用反向传递函数。传输函数根据信道条件动态地改变，以消除或以其他方式减轻电磁干扰（EMI）和串扰条件。在示例性方面，通道上的功率电平之和可以具有最大值。为了遵守这种功率级约束，可以优化传递函数以减少干扰，同时保持在功率级约束内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式