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1. 发明授权

US10635610B1 System and method for serial interface memory using switched architecture 有权
公开(公告)号：US10635610B1
公开(公告)日：2020-04-28
申请号：US16353668
申请日：2019-03-14
申请人： Toshiba Memory Corporation
发明人： Gary James Calder , Benjamin James Kerr , Philip Rose
IPC分类号： G06F13/16 , G06F13/42 , H04L12/741 , G06F13/40
CPC分类号： G06F13/1668 , G06F13/4022 , G06F13/4204 , G06F13/4282 , H04L45/74 , G06F2213/0002
摘要： A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.

2. 发明申请

US20170139869A1 AVIONICS SYSTEM, ARCHITECTURE, AND METHOD 审中-公开
公开(公告)号：US20170139869A1
公开(公告)日：2017-05-18
申请号：US15351412
申请日：2016-11-14
申请人： Sandel Avionics, Inc.
发明人： Gerald J. Block , Delmar M. Fadden , John Morton, III
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4068 , G06F11/1004 , G06F13/4204 , G08G5/025
摘要： Systems and methods according to present principles provide a test architecture which is designed to support software and hardware testing in an automated environment. Systems and methods are described which include a functional definition and architecture of the test system including the host environment, host-user interface, test scripts, host-to-target communications, target test module, target test shell, target commands and other supporting aspects.

3. 发明申请

US20170052519A1 FORMING A LOGICAL MICROCONTROLLER FROM AT LEAST TWO PHYSICAL MICROCONTROLLERS ON A COMMON SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：在通用半导体基板上形成来自最少两个物理微控制器的逻辑微控制器
公开(公告)号：US20170052519A1
公开(公告)日：2017-02-23
申请号：US15306937
申请日：2015-02-24
申请人： Robert Bosch GmbH
发明人： Axel Aue , Hans-Walter Schmitt
IPC分类号： G05B19/042 , G06F13/42 , G06F13/40
CPC分类号： G05B19/0421 , G05B2219/2224 , G05B2219/45018 , G06F13/4068 , G06F13/4204 , G06F13/4282
摘要： A system of at least two microcontrollers on a common semiconductor substrate, each of the at least two microcontrollers respectively having one hardware interface, and the at least two microcontrollers being coupled in data-transmitting fashion via the hardware interfaces by a coupling device.
摘要翻译：一种在公共半导体衬底上的至少两个微控制器的系统，所述至少两个微控制器中的每一个分别具有一个硬件接口，并且所述至少两个微控制器通过耦合器件经由所述硬件接口以数据传输方式耦合。

4. 发明授权

US09379791B2 Multiple input multiple output (MIMO) communication systems and methods for chip to chip and intrachip communication 有权
标题翻译：多输入多输出（MIMO）通信系统和芯片到芯片和内部通信的方法
公开(公告)号：US09379791B2
公开(公告)日：2016-06-28
申请号：US14490818
申请日：2014-09-19
申请人： QUALCOMM Incorporated
发明人： RaviKiran Gopalan , Danlu Zhang
IPC分类号： H04B7/02 , H04B7/04 , H04B7/06 , H04B15/00 , G06F13/42 , H04B7/00
CPC分类号： H04B7/0413 , G06F13/4204 , G06F2213/0038 , H04B7/00 , H04B7/0626 , H04B15/00
摘要： Multiple input multiple output (MIMO) communication systems and methods for chip to chip and intrachip communication are disclosed. In one aspect, MIMO techniques that have been applied to wireless communication systems are applied to interchip and intrachip communication systems. In particular, a transfer function is applied at the transmitter, and a reverse transfer function is applied at the receiver. The transfer function dynamically changes based on channel conditions to cancel or otherwise mitigate electromagnetic interference (EMI) and crosstalk conditions. In an exemplary aspect, a sum of power levels across the channels may have a maximum. To abide by such power level constraint, the transfer function may be optimized to reduce interference while remaining within the power level constraint.
摘要翻译：公开了用于芯片到芯片和内部通信的多输入多输出（MIMO）通信系统和方法。在一个方面，已经应用于无线通信系统的MIMO技术被应用于芯片间和内部通信系统。特别地，在发射机处应用传递函数，并且在接收机处应用反向传递函数。传输函数根据信道条件动态地改变，以消除或以其他方式减轻电磁干扰（EMI）和串扰条件。在示例性方面，通道上的功率电平之和可以具有最大值。为了遵守这种功率级约束，可以优化传递函数以减少干扰，同时保持在功率级约束内。

5. 发明授权

US09208119B2 Data transmitting device for adjusting signal transmission, image forming apparatus, data transmission controlling method, and recording medium storing data transmission control program thereof 有权
标题翻译：用于调整信号传输的数据发送装置，图像形成装置，数据传输控制方法以及存储数据传输控制程序的记录介质
公开(公告)号：US09208119B2
公开(公告)日：2015-12-08
申请号：US14074007
申请日：2013-11-07
申请人： Motohiro Kawanabe , Tatsuya Miyadera , Masayuki Hayashi , Yoshinori Shirasaki , Masatoshi Murakami
发明人： Motohiro Kawanabe , Tatsuya Miyadera , Masayuki Hayashi , Yoshinori Shirasaki , Masatoshi Murakami
IPC分类号： G06F3/12 , G06F13/40 , G06F13/42 , H04N1/00
CPC分类号： G06F13/4068 , G06F13/4204
摘要： A data transmitting device is provided. The data transmitting device includes plural bundles of signal lines, each of which includes flatly arranged plural signal lines and which are overlaid in such a manner that surfaces of the bundles of signal lines are contacted with each other while the signal lines extend in a same direction, wherein signal transmission and reception are performed through the signal lines; a transmission timing adjuster to adjust signal transmission timing for each of the plural bundles of signal lines; and a transmission timing controller to perform time division control such that the transmission timing adjuster adjusts the signal transmission timing under the time division control for each of the plural bundles of signal lines.
摘要翻译：提供数据发送装置。数据发送装置包括多条信号线，每条信号线包括平面排列的多个信号线，并且以这样的方式叠加信号线的表面彼此接触，同时信号线沿相同方向延伸其中通过信号线执行信号发送和接收; 发送定时调整器，用于调整所述多个信号线束中的每一个的信号发送定时; 以及发送定时控制器，用于执行时分控制，使得发送定时调整器针对多条信号线中的每一束在时分控制下调整信号发送定时。

6. 发明申请

US20150149665A1 POLLING METHOD OF COMMUNICATION SYSTEM 审中-公开
标题翻译：通信系统的调查方法
公开(公告)号：US20150149665A1
公开(公告)日：2015-05-28
申请号：US14521147
申请日：2014-10-22
申请人： LSIS CO., LTD.
发明人： KMM KI PAEK
IPC分类号： G06F13/22
CPC分类号： G06F13/225 , G06F13/4204
摘要： The present disclosure relates to a polling method of communication system configured to reduce a polling time by receiving responses from a plurality of auxiliary devices using one time of response request signal by a main device during polling, the method including, requesting, by a main device, transmission of response request signals from a plurality of auxiliary devices connected to the main device (request step), determining whether each of the plurality of auxiliary devices is a response object after receiving the response request signal (response object determination step), determining a response order by each of the plurality of auxiliary devices that has determined itself as the response object (response order determination step), and responding, by itself, to the response request after lapse of waiting time in response to its response order (response step).
摘要翻译：本公开涉及一种通信系统的轮询方法，其被配置为通过在轮询期间由主设备使用一次响应请求信号从多个辅助设备接收响应来减少轮询时间，该方法包括由主设备请求从连接到主设备的多个辅助设备发送响应请求信号（请求步骤），在接收到响应请求信号（响应对象确定步骤）之后确定多个辅助设备中的每一个是响应对象，确定一个响应顺序由响应对象（响应顺序确定步骤）决定的多个辅助装置中的每一个，响应于响应顺序（响应步骤）响应等待时间之后的响应请求，。

7. 发明申请

US20140153042A1 DATA TRANSMITTING DEVICE, IMAGE FORMING APPARATUS, DATA TRANSMISSION CONTROLLING METHOD, AND RECORDING MEDIUM STORING DATA TRANSMISSION CONTROL PROGRAM 有权
标题翻译：数据传输设备，图像形成设备，数据传输控制方法和记录媒体存储数据传输控制程序
公开(公告)号：US20140153042A1
公开(公告)日：2014-06-05
申请号：US14074007
申请日：2013-11-07
申请人： Motohiro KAWANABE , Tatsuya MIYADERA , Masayuki HAYASHI , Yoshinori SHIRASAKI , Masatoshi MURAKAMI
发明人： Motohiro KAWANABE , Tatsuya MIYADERA , Masayuki HAYASHI , Yoshinori SHIRASAKI , Masatoshi MURAKAMI
IPC分类号： G06F3/12
CPC分类号： G06F13/4068 , G06F13/4204
摘要： A data transmitting device is provided. The data transmitting device includes plural bundles of signal lines, each of which includes flatly arranged plural signal lines and which are overlaid in such a manner that surfaces of the bundles of signal lines are contacted with each other while the signal lines extend in a same direction, wherein signal transmission and reception are performed through the signal lines; a transmission timing adjuster to adjust signal transmission timing for each of the plural bundles of signal lines; and a transmission timing controller to perform time division control such that the transmission timing adjuster adjusts the signal transmission timing under the time division control for each of the plural bundles of signal lines.
摘要翻译：提供数据发送装置。数据发送装置包括多条信号线，每条信号线包括平面排列的多个信号线，并且以这样的方式叠加信号线的表面彼此接触，同时信号线沿相同方向延伸其中通过信号线执行信号发送和接收; 发送定时调整器，用于调整所述多个信号线束中的每一个的信号发送定时; 以及发送定时控制器，用于执行时分控制，使得发送定时调整器针对多条信号线中的每一束在时分控制下调整信号发送定时。

8. 发明授权

US08581755B2 Multiple word data bus inversion 有权
标题翻译：多字数据总线反转
公开(公告)号：US08581755B2
公开(公告)日：2013-11-12
申请号：US13502474
申请日：2010-10-08
申请人： Aliazam Abbasfar , John Wilson
发明人： Aliazam Abbasfar , John Wilson
IPC分类号： H03M5/00
CPC分类号： H04L25/4915 , G06F13/4072 , G06F13/4204 , G11C7/1006 , H04L25/0272
摘要： A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.
摘要翻译：用于将数据从一个电路传输到另一电路的数据编码方案考虑组合的多个字的汉明权重来确定是否反转要发送的单个字。多字数据编码方案基于组合的多个字中的总HW执行数据反转来执行DBI编码。基于每个单词的个体汉明重量的总和，决定反转或不反转每个多个单词。这种编码的优点在于，当编码数据具有通过宽并行总线从一个电路发送到另一个电路的大量字时，SSO噪声显着降低。

9. 发明申请

US20080148088A1 Architecture for a Physical Interface of a High Speed Front Side Bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US20080148088A1
公开(公告)日：2008-06-19
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F11/00
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

10. 发明授权

US07293126B2 Enhanced structure of extensible time-sharing bus capable of reducing pin number, extending memory capacity, and performing I/O mapping access and block access 失效
标题翻译：增强的可扩展分时总线结构，能够减少引脚数量，扩展内存容量，并执行I / O映射访问和阻止访问
公开(公告)号：US07293126B2
公开(公告)日：2007-11-06
申请号：US11113039
申请日：2005-04-25
申请人： Tung-Tsai Liao , Wen-Zen Shih
发明人： Tung-Tsai Liao , Wen-Zen Shih
IPC分类号： G06F13/00
CPC分类号： G06F13/36 , G06F13/4204
摘要： An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination of two control lines to determine address transfer, data read or data write on the address and data bus, thereby reducing interface pins and obtaining flexible and multiplicative memory.
摘要翻译：可扩展分时总线的增强结构，其基本上使用地址和数据总线进行分时分配，通过微处理器接口和存储器接口在微处理器和存储器之间发送地址和数据，以及两个控制线的逻辑组合以确定地址和数据总线上的地址传输，数据读取或数据写入，从而减少接口引脚并获得灵活和乘法的存储器。

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