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1. 发明授权

US5212374A Method and apparatus for positioning and biasing an electro-optic modulator of an electro-optic imaging system 失效
标题翻译：用于定位和偏移电光成像系统的电光调制器的方法和装置
公开(公告)号：US5212374A
公开(公告)日：1993-05-18
申请号：US804257
申请日：1991-12-04
申请人： James C. Speedy , Francois J. Henley , Hee-June Choi , Michael J. Miller , Ying-Moh Liu
发明人： James C. Speedy , Francois J. Henley , Hee-June Choi , Michael J. Miller , Ying-Moh Liu
IPC分类号： G01R31/302 , G01R19/00 , G01R31/308 , G02F1/13 , G09G3/00 , H01L21/66
CPC分类号： G09G3/006 , G01R31/308 , G02F1/1309
摘要： An imaging method creates a two-dimensional image of a voltage distribution or a capacitance distribution across a surface of a substrate under test using an electro-optic modulator which is positioned and biased with respect to the surface of the substrate. The method involves a first coarse offsite calibrating step to compensate for nonuniformities in the light emerging from the modulator. Then, for each successive portion of the substrate over which the modulator is to detect characteristics of the substrate, the system undergoes a modulator relocating step, a modulator levelling step, a modulator gapping step, a fine onsite calibrating step, and a measuring step. An apparatus is disclosed for levelling the bottom surface of a modulator into a substantially coplanar spacial relationship with a portion of top surface of the underlying substrate being tested monitors light emerging from at least three regions on the top surface of the modulator in order to determine the relative distances of three corresponding regions of the bottom surface of the modulator from the underlying top surface of the substrate being tested. In one embodiment, three transducers are used to control the spacial orientation of the modulator. The method and apparatus see special application in detecting defects in LCD display panels.
摘要翻译：成像方法使用相对于衬底的表面定位和偏置的电光调制器产生跨越被测衬底的表面的电压分布或电容分布的二维图像。该方法涉及第一粗糙非现场校准步骤以补偿从调制器出射的光的不均匀性。然后，对于调制器要在其上检测衬底的特性的衬底的每个连续部分，系统经历调制器重定位步骤，调制器调平步骤，调制器间隔步骤，精细现场校准步骤和测量步骤。公开了一种用于将调制器的底表面平整为与待测试的下层基底的顶表面的一部分基本上共面的空间关系，监测从调制器顶表面上的至少三个区域出射的光，以便确定调制器底表面的三个对应区域与正在测试的衬底的下表面之间的相对距离。在一个实施例中，使用三个换能器来控制调制器的空间取向。该方法和装置在液晶显示面板检测缺陷方面具有特殊应用。

2. 发明授权

US5387788A Method and apparatus for positioning and biasing an electro-optic modulator of an electro-optic imaging system 失效
标题翻译：用于定位和偏置电光成像系统的电光调制器的方法和装置
公开(公告)号：US5387788A
公开(公告)日：1995-02-07
申请号：US27210
申请日：1993-03-05
申请人： Michael J. Miller , Ginetto Addiego , Francois J. Henley
发明人： Michael J. Miller , Ginetto Addiego , Francois J. Henley
IPC分类号： G01R31/302 , G01R19/00 , G01R31/308 , G02F1/13 , G09G3/00 , H01L21/66 , G01J1/20
CPC分类号： G09G3/006 , G01R31/308 , G02F1/1309
摘要： An imaging method creates a two-dimensional image of a voltage distribution or a capacitance distribution of a substrate under test using an electro-optic modulator. A coarse modulator calibration determines the effect of non-uniformities in the modulator and determines a look-up table relating the gap distance between the modulator and the substrate to the intensity of the light emerging from the modulator. A positioning means calibration determines a look-up table relating control voltage to response by the positioning means. The modulator is moved over a portion of the substrate and then undergoes a positioning step, a fine onsite calibrating step, and a measuring step. The positioning step can be accomplished using the intensity of emerging light to determine modulator gap distance, and the response verses control voltage look-up table to determine a control signal to vertically position the modulator. The look-up tables permit the modulator to be position substantially parallel to the substrate at a desired gap distance using one step positioning.
摘要翻译：成像方法使用电光调制器产生被测衬底的电压分布或电容分布的二维图像。粗调制器校准确定调制器中的非均匀性的影响，并且确定将调制器和衬底之间的间隙距离与从调制器出射的光的强度相关联的查找表。定位装置校准确定将控制电压与定位装置的响应相关联的查找表。调制器在衬底的一部分上移动，然后进行定位步骤，精细的现场校准步骤和测量步骤。可以使用出现的光的强度来确定调制器间隙距离并且响应与控制电压查找表的确定步骤，以确定控制信号以垂直定位调制器。查找表允许调制器使用一步定位以所需的间隙距离基本上平行于基板平齐。

3. 发明授权

US5285150A Method and apparatus for testing LCD panel array 失效
公开(公告)号：US5285150A
公开(公告)日：1994-02-08
申请号：US618183
申请日：1990-11-26
申请人： Francois J. Henley , Michael J. Miller
发明人： Francois J. Henley , Michael J. Miller
IPC分类号： G01R31/02 , G01R31/308 , G01R31/317 , G02F1/13 , G09G3/00 , G09G3/36 , G01R31/26
CPC分类号： G09G3/006 , G01R31/308 , G01R31/31724
摘要： A hierarchical testing method is implemented taking advantage of the nature of the most common defects in an LCD panel to achieve fast effective parametric testing of LCD panels and the like. At the first hierarchy of testing, the panel is logically divided into zones and each zone tested in isolation to identify zones having at least one defect. At the next hierarchy, electro-optic assisted zone inspection is performed to identify where within the zone the defects are located. Lastly, every pixel is inspected using a voltage imaging method to determine whether the switching integrity of the pixel is acceptable. The testing apparatus includes a plurality of panel interface devices coupling the panel under test's drive lines and gate lines to a precision measurement unit (PMU). A controller determines the PMU signals and configures the panel interface devices. The PMU monitors select drive lines and gate lines to isolate zones having defects. An electro-optic voltage measurement system is used to identify the location of defects within an isolated zone.

4. 发明授权

US5363037A Method and apparatus for testing LCD panel array 失效
标题翻译： LCD面板阵列测试方法及装置
公开(公告)号：US5363037A
公开(公告)日：1994-11-08
申请号：US83126
申请日：1993-06-25
申请人： Francois J. Henley , Michael J. Miller
发明人： Francois J. Henley , Michael J. Miller
IPC分类号： G01R31/02 , G01R31/308 , G01R31/317 , G02F1/13 , G09G3/00 , G09G3/36 , G01R31/28
CPC分类号： G09G3/006 , G01R31/308 , G01R31/31724
摘要： A hierarchical testing method is implemented taking advantage of the nature of the most common defects in an LCD panel to achieve fast effective parametric testing of LCD panels and the like. At the first hierarchy of testing, the panel is logically divided into zones and each zone tested in isolation to identify zones having at least one defect. At the next hierarchy, electro-optic assisted zone inspection is performed to identify where within the zone the defects are located. Lastly, every pixel is inspected using a voltage imaging method to determine whether the switching integrity of the pixel is acceptable. The testing apparatus includes a plurality of panel interface devices coupling the panel under test's drive lines and gate lines to a precision measurement unit (PMU). A controller determines the PMU signals and configures the panel interface devices. The PMU monitors select drive lines and gate lines to isolate zones having defects. An electro-optic voltage measurement system is used to identify the location of defects within an isolated zone.
摘要翻译：利用LCD面板中最常见缺陷的性质实现分层测试方法，以实现LCD面板等的快速有效参数测试。在第一层测试中，面板在逻辑上分为区域和每个区域隔离测试，以识别具有至少一个缺陷的区域。在下一层次，执行电光辅助区域检查以识别缺陷位于该区域内的哪里。最后，使用电压成像方法检查每个像素，以确定像素的切换完整性是否可接受。测试装置包括多个面板接口装置，将面板被测试的驱动线和栅极线耦合到精密测量单元（PMU）。控制器确定PMU信号并配置面板接口设备。 PMU监视选择驱动线路和栅线以隔离具有缺陷的区域。电光电压测量系统用于识别隔离区内缺陷的位置。

5. 发明授权

US09125646B2 Needle for laparoscopic suturing instrument 有权
标题翻译：针腹腔镜缝合器
公开(公告)号：US09125646B2
公开(公告)日：2015-09-08
申请号：US13295186
申请日：2011-11-14
申请人： James A. Woodard, Jr. , Michael V. Sherrill , Jason R. Lesko , David T. Martin , Katherine J. Schmid , Michael J. Miller , Gary W. Knight , Richard F. Schwemberger , Atul M. Godbole
发明人： James A. Woodard, Jr. , Michael V. Sherrill , Jason R. Lesko , David T. Martin , Katherine J. Schmid , Michael J. Miller , Gary W. Knight , Richard F. Schwemberger , Atul M. Godbole
IPC分类号： A61B17/06 , A61B17/04 , A61B17/062 , A61B17/29
CPC分类号： A61B17/06004 , A61B17/0469 , A61B17/06066 , A61B17/062 , A61B2017/06009 , A61B2017/06019 , A61B2017/06023 , A61B2017/06047 , A61B2017/06052 , A61B2017/0609 , A61B2017/061 , A61B2017/2929
摘要： A surgical needle includes a pair of ends, a mid-region extending between the ends, and at least one grasping feature configured for grasping by a suturing instrument. An end of a suture is secured to the mid-region of the needle in a manner such that the end of the suture defines an oblique angle with at least part of the centerline defined by the mid-region of the needle. The end of the suture may be disposed in a hollow portion of the needle. The grasping feature may include a notch such as a scallop. The suture may be pivotally coupled with the needle via a ball or pin. The needle may have one or more sharp points. The sharp point may include three converging cutting edges, at least two planar surfaces bounded by the three cutting edges, and a rounded surface bounded by two of the three cutting edges.
摘要翻译：外科用针包括一对端部，在端部之间延伸的中间区域，以及构造成用于通过缝合器械夹持的至少一个抓握部件。缝合线的端部以这样的方式固定到针的中间区域，使得缝合线的端部限定与由针的中间区域限定的中心线的至少一部分的倾斜角度。缝线的末端可以设置在针的中空部分中。抓握功能可以包括诸如扇贝的凹口。缝合线可以经由球或针与针枢转地联接。针可能具有一个或多个尖锐点。锐点可以包括三个会聚的切割边缘，由三个切割边界限定的至少两个平面，以及由三个切割边缘中的两个限定的圆形表面。

6. 发明授权

US08368217B2 Integrated circuit package with segregated Tx and Rx data channels 有权
标题翻译：集成电路封装，具有隔离的Tx和Rx数据通道
公开(公告)号：US08368217B2
公开(公告)日：2013-02-05
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

7. 发明申请

US20120267769A1 INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS 有权
标题翻译：集成电路封装与分离的TX和RX数据通道
公开(公告)号：US20120267769A1
公开(公告)日：2012-10-25
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L23/58
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

8. 发明申请

US20120068339A1 VLSI Package for High Performance Integrated Circuit 审中-公开
标题翻译：用于高性能集成电路的VLSI封装
公开(公告)号：US20120068339A1
公开(公告)日：2012-03-22
申请号：US12887298
申请日：2010-09-21
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/50 , G11C5/02 , H01L23/49838 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having functional components, wherein (a) the power lines and the data channels in the package substrate are coupled to the functional components of the substrate by conducting bumps, (b) the conducting balls coupling the data access channels in the PCB to the data channels in the package substrate are located along the edges of the package substrate; and (c) the conducting balls coupling the power lines in the PCB and the power lines in the package substrate are located in an interior portion of the package substrate. Also, an integrated circuit may further include a circuit substrate having active components, including a SerDes circuit at a center portion of the substrate.
摘要翻译：提供封装的集成电路用于放置在提供电力线和数据访问通道的印刷电路板（PCB）层上。封装的集成电路包括：具有数据通道和电源线的封装基板; 具有功能部件的电路基板，其中（a）封装基板中的电源线和数据通道通过传导凸块而耦合到基板的功能部件，（b）将PCB中的数据访问通道耦合到的导电球到封装衬底中的数据通道沿封装衬底的边缘定位; 和（c）将PCB中的电力线和封装衬底中的电力线耦合的导电球位于封装衬底的内部。此外，集成电路还可以包括具有有源部件的电路基板，在基板的中心部分包括SerDes电路。

9. 发明申请

US20120025397A1 Semiconductor Chip Layout 有权
标题翻译：半导体芯片布局
公开(公告)号：US20120025397A1
公开(公告)日：2012-02-02
申请号：US12846763
申请日：2010-07-29
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

10. 发明授权

US08005632B2 Method and apparatus for detecting faults in a current sensing device 有权
标题翻译：用于检测电流感测装置中的故障的方法和装置
公开(公告)号：US08005632B2
公开(公告)日：2011-08-23
申请号：US11936291
申请日：2007-11-07
申请人： Andrew M. Zettel , Jayanthi Padmanabhan , Michael J. Miller
发明人： Andrew M. Zettel , Jayanthi Padmanabhan , Michael J. Miller
IPC分类号： G01R19/00
CPC分类号： G01R35/00 , G01R31/024 , G01R31/2829
摘要： A method and article of manufacture are provided to monitor a sensing system operative to monitor electrical current in a transmission line between an electrical storage device and an electrical machine. The sensing system comprises first and second sensors, operative to monitor first and second ranges of electrical current. The method comprises determining outputs of the first and second sensors are valid, and comparing outputs of the first and second sensors when current is substantially zero. The method comprises comparing magnitudes of the outputs of the first and second sensors when the monitored electrical current, and monitoring polarity of each of the outputs of the first and second sensors.
摘要翻译：提供了一种制造方法和监视感测系统，该感测系统可操作以监测电存储装置和电机之间的传输线路中的电流。感测系统包括第一和第二传感器，用于监视第一和第二电流范围。该方法包括确定第一和第二传感器的输出是有效的，并且当电流基本上为零时，比较第一和第二传感器的输出。该方法包括：当监测的电流和第一和第二传感器的每个输出的监视极性时，比较第一和第二传感器的输出的幅度。

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