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1. 发明申请

US20130313723A1 SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS 有权
标题翻译：带有STAGGERED TX和TX数据线的半导体芯片布局
公开(公告)号：US20130313723A1
公开(公告)日：2013-11-28
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/538
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

2. 发明授权

US08890332B2 Semiconductor chip layout with staggered Tx and Tx data lines 有权
标题翻译：具有交错Tx和Tx数据线的半导体芯片布局
公开(公告)号：US08890332B2
公开(公告)日：2014-11-18
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

3. 发明授权

US08368217B2 Integrated circuit package with segregated Tx and Rx data channels 有权
标题翻译：集成电路封装，具有隔离的Tx和Rx数据通道
公开(公告)号：US08368217B2
公开(公告)日：2013-02-05
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

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