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1. 发明授权

US08368217B2 Integrated circuit package with segregated Tx and Rx data channels 有权
标题翻译：集成电路封装，具有隔离的Tx和Rx数据通道
公开(公告)号：US08368217B2
公开(公告)日：2013-02-05
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

2. 发明授权

US08890332B2 Semiconductor chip layout with staggered Tx and Tx data lines 有权
标题翻译：具有交错Tx和Tx数据线的半导体芯片布局
公开(公告)号：US08890332B2
公开(公告)日：2014-11-18
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

3. 发明申请

US20130313723A1 SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS 有权
标题翻译：带有STAGGERED TX和TX数据线的半导体芯片布局
公开(公告)号：US20130313723A1
公开(公告)日：2013-11-28
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/538
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

4. 发明申请

US20120267769A1 INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS 有权
标题翻译：集成电路封装与分离的TX和RX数据通道
公开(公告)号：US20120267769A1
公开(公告)日：2012-10-25
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L23/58
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

5. 发明授权

US09342471B2 High utilization multi-partitioned serial memory 有权
标题翻译：高利用率多分区串行存储器
公开(公告)号：US09342471B2
公开(公告)日：2016-05-17
申请号：US12697141
申请日：2010-01-29
申请人： Michael J. Miller , Richard S. Roy
发明人： Michael J. Miller , Richard S. Roy
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1647
摘要： A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.
摘要翻译：一种存储装置，包括在第一多个串行链路上接收指令和输入数据的输入接口。指令和输入数据在存储器件上反序列化，并被提供给存储器控制器。存储器控制器响应于接收的指令启动对存储器内核的访问。存储器核心包括以循环和重叠的方式访问的多个存储器分区。这允许每个存储器分区以比串行链路更低的频率工作，同时正确地维护接收到的指令。以同步方式执行对存储设备的访问，其中每个访问呈现已知的固定等待时间。

6. 发明授权

US08901747B2 Semiconductor chip layout 有权
标题翻译：半导体芯片布局
公开(公告)号：US08901747B2
公开(公告)日：2014-12-02
申请号：US12846763
申请日：2010-07-29
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L29/40 , H01L23/50
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

7. 发明申请

US20110191548A1 High Utilization Multi-Partitioned Serial Memory 有权
标题翻译：高利用多分区串行存储器
公开(公告)号：US20110191548A1
公开(公告)日：2011-08-04
申请号：US12697141
申请日：2010-01-29
申请人： Michael J. Miller , Richard S. Roy
发明人： Michael J. Miller , Richard S. Roy
IPC分类号： G06F12/08 , G06F13/12
CPC分类号： G06F13/1647
摘要： A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.
摘要翻译：一种存储装置，包括在第一多个串行链路上接收指令和输入数据的输入接口。指令和输入数据在存储器件上反序列化，并被提供给存储器控制器。存储器控制器响应于接收的指令启动对存储器内核的访问。存储器核心包括以循环和重叠的方式访问的多个存储器分区。这允许每个存储器分区以比串行链路更低的频率工作，同时正确地维护接收到的指令。以同步方式执行对存储设备的访问，其中每个访问呈现已知的固定等待时间。

8. 发明授权

US09125646B2 Needle for laparoscopic suturing instrument 有权
标题翻译：针腹腔镜缝合器
公开(公告)号：US09125646B2
公开(公告)日：2015-09-08
申请号：US13295186
申请日：2011-11-14
申请人： James A. Woodard, Jr. , Michael V. Sherrill , Jason R. Lesko , David T. Martin , Katherine J. Schmid , Michael J. Miller , Gary W. Knight , Richard F. Schwemberger , Atul M. Godbole
发明人： James A. Woodard, Jr. , Michael V. Sherrill , Jason R. Lesko , David T. Martin , Katherine J. Schmid , Michael J. Miller , Gary W. Knight , Richard F. Schwemberger , Atul M. Godbole
IPC分类号： A61B17/06 , A61B17/04 , A61B17/062 , A61B17/29
CPC分类号： A61B17/06004 , A61B17/0469 , A61B17/06066 , A61B17/062 , A61B2017/06009 , A61B2017/06019 , A61B2017/06023 , A61B2017/06047 , A61B2017/06052 , A61B2017/0609 , A61B2017/061 , A61B2017/2929
摘要： A surgical needle includes a pair of ends, a mid-region extending between the ends, and at least one grasping feature configured for grasping by a suturing instrument. An end of a suture is secured to the mid-region of the needle in a manner such that the end of the suture defines an oblique angle with at least part of the centerline defined by the mid-region of the needle. The end of the suture may be disposed in a hollow portion of the needle. The grasping feature may include a notch such as a scallop. The suture may be pivotally coupled with the needle via a ball or pin. The needle may have one or more sharp points. The sharp point may include three converging cutting edges, at least two planar surfaces bounded by the three cutting edges, and a rounded surface bounded by two of the three cutting edges.
摘要翻译：外科用针包括一对端部，在端部之间延伸的中间区域，以及构造成用于通过缝合器械夹持的至少一个抓握部件。缝合线的端部以这样的方式固定到针的中间区域，使得缝合线的端部限定与由针的中间区域限定的中心线的至少一部分的倾斜角度。缝线的末端可以设置在针的中空部分中。抓握功能可以包括诸如扇贝的凹口。缝合线可以经由球或针与针枢转地联接。针可能具有一个或多个尖锐点。锐点可以包括三个会聚的切割边缘，由三个切割边界限定的至少两个平面，以及由三个切割边缘中的两个限定的圆形表面。

9. 发明申请

US20120068339A1 VLSI Package for High Performance Integrated Circuit 审中-公开
标题翻译：用于高性能集成电路的VLSI封装
公开(公告)号：US20120068339A1
公开(公告)日：2012-03-22
申请号：US12887298
申请日：2010-09-21
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/50 , G11C5/02 , H01L23/49838 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having functional components, wherein (a) the power lines and the data channels in the package substrate are coupled to the functional components of the substrate by conducting bumps, (b) the conducting balls coupling the data access channels in the PCB to the data channels in the package substrate are located along the edges of the package substrate; and (c) the conducting balls coupling the power lines in the PCB and the power lines in the package substrate are located in an interior portion of the package substrate. Also, an integrated circuit may further include a circuit substrate having active components, including a SerDes circuit at a center portion of the substrate.
摘要翻译：提供封装的集成电路用于放置在提供电力线和数据访问通道的印刷电路板（PCB）层上。封装的集成电路包括：具有数据通道和电源线的封装基板; 具有功能部件的电路基板，其中（a）封装基板中的电源线和数据通道通过传导凸块而耦合到基板的功能部件，（b）将PCB中的数据访问通道耦合到的导电球到封装衬底中的数据通道沿封装衬底的边缘定位; 和（c）将PCB中的电力线和封装衬底中的电力线耦合的导电球位于封装衬底的内部。此外，集成电路还可以包括具有有源部件的电路基板，在基板的中心部分包括SerDes电路。

10. 发明申请

US20120025397A1 Semiconductor Chip Layout 有权
标题翻译：半导体芯片布局
公开(公告)号：US20120025397A1
公开(公告)日：2012-02-02
申请号：US12846763
申请日：2010-07-29
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

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