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1. 发明申请

US20150039795A1 SYSTEM INTERCONNECTION, SYSTEM-ON-CHIP HAVING THE SAME, AND METHOD OF DRIVING THE SYSTEM-ON-CHIP 有权
标题翻译：系统互连，具有该系统的片上系统，以及驱动片上系统的方法
公开(公告)号：US20150039795A1
公开(公告)日：2015-02-05
申请号：US14320993
申请日：2014-07-01
申请人： Jae-Young Hur , Hyun-Joon Kang , Sung-Min Hong
发明人： Jae-Young Hur , Hyun-Joon Kang , Sung-Min Hong
IPC分类号： G06F9/46 , G06F13/16 , G06F13/12
CPC分类号： G06F13/1621 , G06F13/4022 , G06F13/4059
摘要： Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.
摘要翻译：提供了一种驱动片上系统（SOC）的方法。该方法包括将第一事务添加到列表中，将第一事务分配到第一时隙，确定第二事务是否是冗余的，以及将第二事务添加到列表中，并且当确定第二事务被确定为第一事务时，将第二事务分配给第一时隙第二个事务是多余的。因此，SOC可以提高突出的能力并提高系统互连的性能。

2. 发明申请

US20120117286A1 Interface Devices And Systems Including The Same 审中-公开
标题翻译：接口设备和系统包括它
公开(公告)号：US20120117286A1
公开(公告)日：2012-05-10
申请号：US13287339
申请日：2011-11-02
申请人： Jae-Geun Yun , Jun-Hyung Um , Hyun-Uk Jung , Sung-Min Hong , Jung-Sik Lee , Hyun-Joon Kang , Ling Ling Liao , Woo-Cheol Kwon
发明人： Jae-Geun Yun , Jun-Hyung Um , Hyun-Uk Jung , Sung-Min Hong , Jung-Sik Lee , Hyun-Joon Kang , Ling Ling Liao , Woo-Cheol Kwon
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： An interface device includes a transaction management unit, a buffer unit and a selection circuit. The transaction management unit selectively splits a transaction of a master device into a first sub-transaction and at least one remaining sub-transaction based on a size of the transaction. The buffer unit stores the remaining sub-transaction. The selection circuit selects one of the first sub-transaction and an output of the buffer unit in response to a select control signal.
摘要翻译：接口设备包括交易管理单元，缓冲单元和选择电路。交易管理单元基于交易的大小有选择地将主设备的交易分成第一子交易和至少一个剩余的子交易。缓冲单元存储剩余的子事务。选择电路响应于选择控制信号选择第一子事务和缓冲器单元的输出之一。

3. 发明申请

US20120131246A1 SYSTEM-ON-CHIP AND DATA ARBITRATION METHOD THEREOF 有权
标题翻译：系统片上和数据仲裁方法
公开(公告)号：US20120131246A1
公开(公告)日：2012-05-24
申请号：US13276748
申请日：2011-10-19
申请人： Bub-chul Jeong , Jaegeun Yun , Junhyung Um , Jung-Sik Lee , Hyun-Joon Kang , Sung-Min Hong , Ling Ling Liao
发明人： Bub-chul Jeong , Jaegeun Yun , Junhyung Um , Jung-Sik Lee , Hyun-Joon Kang , Sung-Min Hong , Ling Ling Liao
IPC分类号： G06F13/00
CPC分类号： G06F13/4217 , G06F2213/0038
摘要： A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master.An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.
摘要翻译：片上系统半导体器件包括被配置为发出具有事务ID的请求的第一主设备，被配置为响应于该请求而提供数据的多个从设备，以及互连器，被配置为包括从接口，向所述主接口提供所述请求，并且基于所述第一主设备的操作特性向所述第一主设备提供响应数据。将从多个从设备提供的多个响应数据传送到主设备的互连器的仲裁方法包括基于主设备的操作特性选择多个仲裁模式中的一个; 并以与所选仲裁模式对应的传送优先级确定的顺序传送响应数据。

4. 发明申请

US20120089758A1 System On Chip Keeping Load Balance And Load Balancing Method Thereof 审中-公开
标题翻译：系统片上保持负载平衡和负载平衡方法
公开(公告)号：US20120089758A1
公开(公告)日：2012-04-12
申请号：US13178666
申请日：2011-07-08
申请人： Jaegeun Yun , Bub-chul Jeong , Junhyung Um , Hyun-Joon Kang , Sung-Min Hong , LIAOLINGLING
发明人： Jaegeun Yun , Bub-chul Jeong , Junhyung Um , Hyun-Joon Kang , Sung-Min Hong , LIAOLINGLING
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： At least one example embodiment discloses a System on Chip (SoC). The SoC includes a master block, a plurality of slave blocks configured to operate in response to a request from the master block, and an interconnect block configured to deliver transactions occurring in the master block to the plurality of slave blocks through a plurality of transfer paths. The interconnect block is configured to monitor load information of the plurality of transfer paths and select one of the plurality of transfer paths according to the load information.
摘要翻译：至少一个示例性实施例公开了片上系统（SoC）。 SoC包括主块，被配置为响应于来自主块的请求而操作的多个从块，以及被配置为通过多个传输路径将在主块中发生的事务传递到多个从块的互连块。互连块被配置为监视多个传送路径的负载信息，并且根据负载信息选择多个传送路径中的一个。

5. 发明授权

US08819310B2 System-on-chip and data arbitration method thereof 有权
标题翻译：片上系统和数据仲裁方法
公开(公告)号：US08819310B2
公开(公告)日：2014-08-26
申请号：US13276748
申请日：2011-10-19
申请人： Bub-chul Jeong , Jaegeun Yun , Junhyung Um , Jung-Sik Lee , Hyun-Joon Kang , Sung-Min Hong , Ling Ling Liao
发明人： Bub-chul Jeong , Jaegeun Yun , Junhyung Um , Jung-Sik Lee , Hyun-Joon Kang , Sung-Min Hong , Ling Ling Liao
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4217 , G06F2213/0038
摘要： A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master.An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.
摘要翻译：片上系统半导体器件包括被配置为发出具有事务ID的请求的第一主设备，被配置为响应于该请求而提供数据的多个从设备，以及互连器，被配置为包括从接口，向所述主接口提供所述请求，并且基于所述第一主设备的操作特性向所述第一主设备提供响应数据。将从多个从设备提供的多个响应数据传送到主设备的互连器的仲裁方法包括基于主设备的操作特性选择多个仲裁模式中的一个; 并以与所选仲裁模式对应的传送优先级确定的顺序传送响应数据。

6. 发明授权

US08443122B2 Asynchronous upsizing circuit in data processing system 有权
标题翻译：数据处理系统中的异步升压电路
公开(公告)号：US08443122B2
公开(公告)日：2013-05-14
申请号：US12917854
申请日：2010-11-02
申请人： JaeGeun Yun , Junhyung Um , Woo-Cheol Kwon , Hyun-Joon Kang , Bub-chul Jeong
发明人： JaeGeun Yun , Junhyung Um , Woo-Cheol Kwon , Hyun-Joon Kang , Bub-chul Jeong
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4059
摘要： An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.
摘要翻译：数据处理系统中的异步增大电路。异步升压电路包括异步封隔器和异步解包器。异步封隔器包括通常用于异步桥的写入缓冲器，并且用于增大和缓冲写通道数据; 以及第一和第二异步打包控制器，分别根据第一和第二时钟控制在突发写入操作期间输入/输出到写入缓冲器的写入通道数据的通道压缩。异步解包器包括通常用于异步网桥的读缓冲器，并用于增大和缓冲读通道数据; 以及分别针对在突发读取操作期间从读取缓冲器输入/输出的读通道数据，分别根据第一和第二时钟控制信道压缩的第一和第二异步解包控制器。

7. 发明申请

US20120246368A1 SYSTEM ON CHIP IMPROVING DATA TRAFFIC AND OPERATING METHOD THEREOF 有权
标题翻译：芯片系统改善数据流量及其操作方法
公开(公告)号：US20120246368A1
公开(公告)日：2012-09-27
申请号：US13427096
申请日：2012-03-22
申请人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
发明人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
IPC分类号： G06F13/40
CPC分类号： G06F13/3625 , G06F13/4022
摘要： A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.
摘要翻译：片上系统（SoC）包括第一主机，从机，发送主机的第一命令和从机的第一响应的总线开关以及连接在第一主机和总线交换机之间的第一优先级控制器。第一优先级控制器基于第一命令和第一响应来测量第一带宽和第一延迟中的至少一个，并且根据测量结果中的至少一个来调整第一命令的优先级。

8. 发明申请

US20150206560A1 CIRCUIT FOR CONTROLLING WRITE LEVELING OF A TARGET MODULE AND A METHOD THEREOF 有权
标题翻译：用于控制目标模块的写入电平的电路及其方法
公开(公告)号：US20150206560A1
公开(公告)日：2015-07-23
申请号：US14573379
申请日：2014-12-17
申请人： Hyun-Joon Kang , Yongchun Kim , Sungkook Shin
发明人： Hyun-Joon Kang , Yongchun Kim , Sungkook Shin
IPC分类号： G11C7/10 , G01R31/3193
CPC分类号： G11C29/023 , G11C7/1066 , G11C7/1069 , G11C7/222 , G11C29/022 , G11C29/028
摘要： A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.
摘要翻译：一种写入调平控制方法，其包括在对准参考表中登记与存储器模块的类型对应的数据相关信号（DRS）参考延迟值; 将写平均相关信号发送到安装在目标板上的第一类型的存储器模块; 检测时钟信号与从所安装的存储器模块上的存储器件接收到的数据相关信号之间的时序偏差; 以及如果对应的定时偏移在第一范围之外，则基于与所安装的存储器模块对应的DRS参考延迟值，调整发送到所安装的存储器模块的存储器件的数据相关信号的延迟。

9. 发明授权

US08943249B2 System on chip improving data traffic and operating method thereof 有权
标题翻译：片上系统提高数据流量及其操作方法
公开(公告)号：US08943249B2
公开(公告)日：2015-01-27
申请号：US13427096
申请日：2012-03-22
申请人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
发明人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
IPC分类号： G06F13/00 , G06F13/362 , G06F13/40
CPC分类号： G06F13/3625 , G06F13/4022
摘要： A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.
摘要翻译：片上系统（SoC）包括第一主机，从机，发送主机的第一命令和从机的第一响应的总线开关以及连接在第一主机和总线交换机之间的第一优先级控制器。第一优先级控制器基于第一命令和第一响应来测量第一带宽和第一延迟中的至少一个，并且根据测量结果中的至少一个来调整第一命令的优先级。

10. 发明申请

US20110131350A1 ASYNCHRONOUS UPSIZING CIRCUIT IN DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中异步升压电路
公开(公告)号：US20110131350A1
公开(公告)日：2011-06-02
申请号：US12917854
申请日：2010-11-02
申请人： JaeGeun Yun , Junhyung Um , WooCheol Kwon , Hyun-Joon Kang , Bub-chul Jeong
发明人： JaeGeun Yun , Junhyung Um , WooCheol Kwon , Hyun-Joon Kang , Bub-chul Jeong
IPC分类号： G06F5/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.
摘要翻译：数据处理系统中的异步增大电路。异步升压电路包括异步封隔器和异步解包器。异步封隔器包括通常用于异步桥的写入缓冲器，并且用于增大和缓冲写通道数据; 以及第一和第二异步打包控制器，分别根据第一和第二时钟控制在突发写入操作期间输入/输出到写入缓冲器的写入通道数据的通道压缩。异步解包器包括通常用于异步网桥的读缓冲器，并用于增大和缓冲读通道数据; 以及分别针对在突发读取操作期间从读取缓冲器输入/输出的读通道数据，分别根据第一和第二时钟控制信道压缩的第一和第二异步解包控制器。

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