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1. 发明授权

US08943249B2 System on chip improving data traffic and operating method thereof 有权
标题翻译：片上系统提高数据流量及其操作方法
公开(公告)号：US08943249B2
公开(公告)日：2015-01-27
申请号：US13427096
申请日：2012-03-22
申请人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
发明人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
IPC分类号： G06F13/00 , G06F13/362 , G06F13/40
CPC分类号： G06F13/3625 , G06F13/4022
摘要： A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.
摘要翻译：片上系统（SoC）包括第一主机，从机，发送主机的第一命令和从机的第一响应的总线开关以及连接在第一主机和总线交换机之间的第一优先级控制器。第一优先级控制器基于第一命令和第一响应来测量第一带宽和第一延迟中的至少一个，并且根据测量结果中的至少一个来调整第一命令的优先级。

2. 发明申请

US20130138848A1 ASYNCHRONOUS BRIDGE 有权
标题翻译：异步桥
公开(公告)号：US20130138848A1
公开(公告)日：2013-05-30
申请号：US13617734
申请日：2012-09-14
申请人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
发明人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
IPC分类号： G06F13/38
CPC分类号： G06F13/405
摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.
摘要翻译：异步桥包括传输单元和接收单元。发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入数据，按读取地址指示。接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。

3. 发明申请

US20120221754A1 SYSTEM ON CHIP BUS SYSTEM AND A METHOD OF OPERATING THE BUS SYSTEM 有权
标题翻译：系统在芯片总线系统和一种操作总线系统的方法
公开(公告)号：US20120221754A1
公开(公告)日：2012-08-30
申请号：US13403568
申请日：2012-02-23
申请人： Sung-min Hong , Jae-geun Yun
发明人： Sung-min Hong , Jae-geun Yun
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/42 , G06F2213/0038
摘要： A bus system of a system on chip (SoC) includes a first and a second masters, a first slave, and a first and a second control modules. The control modules generates a first and a second access control state signals in response to a first locking access preparation request signal from a corresponding master. The access control signals are broadcasted between the first and the second control modules through a communication channel.A method of operating a bus system in a locked access mode includes allowing one of masters to access one of slaves through a control module and restricting other masters from accessing the one of slaves through other control modules connecting the other masters and the one of slaves in accordance with a control state signal.
摘要翻译：片上系统（SoC）的总线系统包括第一和第二主机，第一从机以及第一和第二控制模块。控制模块响应于来自相应主机的第一锁定访问准备请求信号而产生第一和第二访问控制状态信号。访问控制信号通过通信信道在第一和第二控制模块之间广播。以锁定访问模式操作总线系统的方法包括允许主机中的一个主机通过控制模块访问从站中的一个，并且通过控制模块的其中一个主机和其他主机之间的其他控制模块限制其他主机访问从站中的一个根据控制状态信号。

4. 发明授权

US08165866B2 Emulation system 失效
标题翻译：仿真系统
公开(公告)号：US08165866B2
公开(公告)日：2012-04-24
申请号：US11838017
申请日：2007-08-13
申请人： Chi-Ho Cha , Hoon-Sang Jin , Jae-Geun Yun
发明人： Chi-Ho Cha , Hoon-Sang Jin , Jae-Geun Yun
IPC分类号： G06F9/455
CPC分类号： G06F11/3652
摘要： An emulation system includes a controller, an emulation calculator, an emulation storage unit, and an interface unit. The emulation calculator includes a device under test (DUT) and emulates the DUT. The emulation storage unit stores emulation data of the DUT emulated by the emulation calculator under the control of the controller. The interface unit distributes and transfers the emulation data to a plurality of computers under the control of the controller.
摘要翻译：仿真系统包括控制器，仿真计算器，仿真存储单元和接口单元。仿真计算器包括被测设备（DUT）并仿真DUT。仿真存储单元在控制器的控制下存储由仿真计算器仿真的DUT的仿真数据。接口单元在控制器的控制下将仿真数据分发并传送到多台计算机。

5. 发明申请

US20080046228A1 Emulation System 失效
标题翻译：仿真系统
公开(公告)号：US20080046228A1
公开(公告)日：2008-02-21
申请号：US11838017
申请日：2007-08-13
申请人： Chi-Ho Cha , Hoon-Sang Jin , Jae-Geun Yun
发明人： Chi-Ho Cha , Hoon-Sang Jin , Jae-Geun Yun
IPC分类号： G06F9/455
CPC分类号： G06F11/3652
摘要： An emulation system includes a controller, an emulation calculator, an emulation storage unit, and an interface unit. The emulation calculator includes a device under test (DUT) and emulates the DUT. The emulation storage unit stores emulation data of the DUT emulated by the emulation calculator under the control of the controller. The interface unit distributes and transfers the emulation data to a plurality of computers under the control of the controller.
摘要翻译：仿真系统包括控制器，仿真计算器，仿真存储单元和接口单元。仿真计算器包括被测设备（DUT）并仿真DUT。仿真存储单元在控制器的控制下存储由仿真计算器仿真的DUT的仿真数据。接口单元在控制器的控制下将仿真数据分发并传送到多台计算机。

6. 发明授权

US08819325B2 Interface device and system including the same 有权
标题翻译：接口设备和系统包括相同的
公开(公告)号：US08819325B2
公开(公告)日：2014-08-26
申请号：US13368353
申请日：2012-02-08
申请人： Jae-Geun Yun , Bub-Chul Jeong
发明人： Jae-Geun Yun , Bub-Chul Jeong
IPC分类号： G06F13/00
CPC分类号： G06F13/36 , G06F13/1642
摘要： An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits.
摘要翻译：接口设备包括请求队列和请求队列管理器。请求队列包括被配置为从至少一个主设备接收相应请求并且使用对应的占用位来指示是否包括相应的请求的多个元件。请求队列管理器被配置为至少基于占用比特来管理请求队列。

7. 发明申请

US20120159037A1 MEMORY INTERLEAVING DEVICE AND METHOD USING REORDER BUFFER 有权
标题翻译：存储器交互设备和使用REORDER BUFFER的方法
公开(公告)号：US20120159037A1
公开(公告)日：2012-06-21
申请号：US13323162
申请日：2011-12-12
申请人： Woo Cheol KWON , Jae Geun Yun , Sung-Min Hong
发明人： Woo Cheol KWON , Jae Geun Yun , Sung-Min Hong
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F13/364
摘要： A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.
摘要翻译：存储器交错设备包括从接口，主接口和交叉开关。从接口通过片上网络与主控知识产权相连接。主接口与从属知识产权相连。交叉开关将从接口与主接口相连。存储器交错装置将从主知识产权的请求发送到从属知识产权，分别接收来自从属知识产权的请求的数据或响应，并以请求的顺序将数据或响应发送到主知识产权被收到

8. 发明申请

US20110276735A1 INTERCONNECT, BUS SYSTEM WITH INTERCONNECT AND BUS SYSTEM OPERATING METHOD 有权
标题翻译：具有互连和总线系统工作方式的互连，总线系统
公开(公告)号：US20110276735A1
公开(公告)日：2011-11-10
申请号：US13050405
申请日：2011-03-17
申请人： Joon-Woo CHO , Jong Ho ROH , Jae Geun YUN , Sung-Min HONG
发明人： Joon-Woo CHO , Jong Ho ROH , Jae Geun YUN , Sung-Min HONG
IPC分类号： G06F13/16
CPC分类号： G06F13/368 , G06F12/0607 , G06F13/4022
摘要： Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.
摘要翻译：提供互连，具有互连的总线系统和总线系统操作方法。总线系统包括主站，主站的从站访问和互连。响应于由主机提供的主地址中标识的选择位，互连将主机与从机连接。

9. 发明授权

US09003092B2 System on chip bus system and a method of operating the bus system 有权
标题翻译：系统片上总线系统和一种操作总线系统的方法
公开(公告)号：US09003092B2
公开(公告)日：2015-04-07
申请号：US13403568
申请日：2012-02-23
申请人： Sung-min Hong , Jae-geun Yun
发明人： Sung-min Hong , Jae-geun Yun
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/00 , G06F13/42 , G06F2213/0038
摘要： A bus system of a system on chip (SoC) includes a first and a second masters, a first slave, and a first and a second control modules. The control modules generates a first and a second access control state signals in response to a first locking access preparation request signal from a corresponding master. The access control signals are broadcasted between the first and the second control modules through a communication channel.A method of operating a bus system in a locked access mode includes allowing one of masters to access one of slaves through a control module and restricting other masters from accessing the one of slaves through other control modules connecting the other masters and the one of slaves in accordance with a control state signal.
摘要翻译：片上系统（SoC）的总线系统包括第一和第二主机，第一从机以及第一和第二控制模块。控制模块响应于来自相应主机的第一锁定访问准备请求信号而产生第一和第二访问控制状态信号。访问控制信号通过通信信道在第一和第二控制模块之间广播。以锁定访问模式操作总线系统的方法包括允许主机中的一个主机通过控制模块访问从站中的一个，并且通过控制模块的其中一个主机和其他主机之间的其他控制模块限制其他主机访问从站中的一个根据控制状态信号。

10. 发明授权

US08886861B2 Memory interleaving device to re-order messages from slave IPS and a method of using a reorder buffer to re-order messages from slave IPS 有权
标题翻译：内存交错设备重新排序来自从IPS的消息，以及使用重新排序缓冲区重新排序来自从属IPS的消息的方法
公开(公告)号：US08886861B2
公开(公告)日：2014-11-11
申请号：US13323162
申请日：2011-12-12
申请人： Woo Cheol Kwon , Jae Geun Yun , Sung-Min Hong
发明人： Woo Cheol Kwon , Jae Geun Yun , Sung-Min Hong
IPC分类号： G06F13/00 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4022 , G06F13/364
摘要： A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.
摘要翻译：存储器交错设备包括从接口，主接口和交叉开关。从接口通过片上网络与主控知识产权相连接。主接口与从属知识产权相连。交叉开关将从接口与主接口相连。存储器交错装置将从主知识产权的请求发送到从属知识产权，分别接收来自从属知识产权的请求的数据或响应，并以请求的顺序将数据或响应发送到主知识产权被收到

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