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1. 发明授权

US08943249B2 System on chip improving data traffic and operating method thereof 有权
标题翻译：片上系统提高数据流量及其操作方法
公开(公告)号：US08943249B2
公开(公告)日：2015-01-27
申请号：US13427096
申请日：2012-03-22
申请人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
发明人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
IPC分类号： G06F13/00 , G06F13/362 , G06F13/40
CPC分类号： G06F13/3625 , G06F13/4022
摘要： A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.
摘要翻译：片上系统（SoC）包括第一主机，从机，发送主机的第一命令和从机的第一响应的总线开关以及连接在第一主机和总线交换机之间的第一优先级控制器。第一优先级控制器基于第一命令和第一响应来测量第一带宽和第一延迟中的至少一个，并且根据测量结果中的至少一个来调整第一命令的优先级。

2. 发明申请

US20120246368A1 SYSTEM ON CHIP IMPROVING DATA TRAFFIC AND OPERATING METHOD THEREOF 有权
标题翻译：芯片系统改善数据流量及其操作方法
公开(公告)号：US20120246368A1
公开(公告)日：2012-09-27
申请号：US13427096
申请日：2012-03-22
申请人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
发明人： Woo Cheol Kwon , Jae Geun Yun , Bub-Chul Jeong , Jun Hyung Um , Hyun-Joon Kang
IPC分类号： G06F13/40
CPC分类号： G06F13/3625 , G06F13/4022
摘要： A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.
摘要翻译：片上系统（SoC）包括第一主机，从机，发送主机的第一命令和从机的第一响应的总线开关以及连接在第一主机和总线交换机之间的第一优先级控制器。第一优先级控制器基于第一命令和第一响应来测量第一带宽和第一延迟中的至少一个，并且根据测量结果中的至少一个来调整第一命令的优先级。

3. 发明授权

US08819325B2 Interface device and system including the same 有权
标题翻译：接口设备和系统包括相同的
公开(公告)号：US08819325B2
公开(公告)日：2014-08-26
申请号：US13368353
申请日：2012-02-08
申请人： Jae-Geun Yun , Bub-Chul Jeong
发明人： Jae-Geun Yun , Bub-Chul Jeong
IPC分类号： G06F13/00
CPC分类号： G06F13/36 , G06F13/1642
摘要： An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits.
摘要翻译：接口设备包括请求队列和请求队列管理器。请求队列包括被配置为从至少一个主设备接收相应请求并且使用对应的占用位来指示是否包括相应的请求的多个元件。请求队列管理器被配置为至少基于占用比特来管理请求队列。

4. 发明申请

US20130138848A1 ASYNCHRONOUS BRIDGE 有权
标题翻译：异步桥
公开(公告)号：US20130138848A1
公开(公告)日：2013-05-30
申请号：US13617734
申请日：2012-09-14
申请人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
发明人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
IPC分类号： G06F13/38
CPC分类号： G06F13/405
摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.
摘要翻译：异步桥包括传输单元和接收单元。发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入数据，按读取地址指示。接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。

5. 发明授权

US09183170B2 Asynchronous bridge 有权
标题翻译：异步桥
公开(公告)号：US09183170B2
公开(公告)日：2015-11-10
申请号：US13617734
申请日：2012-09-14
申请人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
发明人： Bub-Chul Jeong , Jae Geun Yun , Jae Gon Lee , Soo Wan Hong
IPC分类号： G06F3/00 , G06F13/40
CPC分类号： G06F13/405
摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.
摘要翻译：异步桥包括传输单元和接收单元。发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入数据，按读取地址指示。接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。

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