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1. 发明申请

US20120045901A1 METHOD OF FORMING A PATTERN STRUCTURE FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案结构的方法
公开(公告)号：US20120045901A1
公开(公告)日：2012-02-23
申请号：US13212349
申请日：2011-08-18
申请人： JONG-HYUK KIM , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
发明人： JONG-HYUK KIM , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816
摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.
摘要翻译：在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而改善对准边缘。掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

2. 发明授权

US08759224B2 Method of forming a pattern structure for a semiconductor device 有权
标题翻译：形成半导体器件的图案结构的方法
公开(公告)号：US08759224B2
公开(公告)日：2014-06-24
申请号：US13212349
申请日：2011-08-18
申请人： Jong-Hyuk Kim , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
发明人： Jong-Hyuk Kim , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816
摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.
摘要翻译：在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而提高对准边缘。掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

3. 发明授权

US07344944B2 Non-volatile memory device and fabricating method thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07344944B2
公开(公告)日：2008-03-18
申请号：US11341073
申请日：2006-01-27
申请人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
发明人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11534 , H01L29/42328
摘要： A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.
摘要翻译：非易失性存储器件包括栅极线，栅极线包括依次堆叠的栅极介电层，底部栅极图案，栅极间电介质和顶栅极图案。栅极间电介质的宽度比底栅图案的宽度窄。

4. 发明申请

US20050012140A1 EEPROM device having selecting transistors and method of fabricating the same 有权
标题翻译：具有选择晶体管的EEPROM器件及其制造方法
公开(公告)号：US20050012140A1
公开(公告)日：2005-01-20
申请号：US10891803
申请日：2004-07-14
申请人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
IPC分类号： H01L21/8247 , G11C11/34 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.
摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

5. 发明授权

US07018894B2 EEPROM device having selecting transistors and method of fabricating the same 有权
标题翻译：具有选择晶体管的EEPROM器件及其制造方法
公开(公告)号：US07018894B2
公开(公告)日：2006-03-28
申请号：US10891803
申请日：2004-07-14
申请人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.
摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

6. 发明授权

US06376876B1 NAND-type flash memory devices and methods of fabricating the same 有权
标题翻译： NAND型闪存器件及其制造方法
公开(公告)号：US06376876B1
公开(公告)日：2002-04-23
申请号：US09678917
申请日：2000-10-04
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur
IPC分类号： H01L2978
CPC分类号： H01L27/11521 , H01L27/115
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要翻译：提供了NAND型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

7. 发明申请

US20060128070A1 Non-volatile memory device and fabricating method thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060128070A1
公开(公告)日：2006-06-15
申请号：US11341073
申请日：2006-01-27
申请人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
发明人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11534 , H01L29/42328
摘要： A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.
摘要翻译：非易失性存储器件包括栅极线，栅极线包括依次堆叠的栅极介电层，底部栅极图案，栅极间电介质和顶栅极图案。栅极间电介质的宽度比底栅图案的宽度窄。

8. 发明申请

US20060113547A1 Methods of fabricating memory devices including fuses and load resistors in a peripheral circuit region 审中-公开
标题翻译：在外围电路区域中制造包括熔丝和负载电阻的存储器件的方法
公开(公告)号：US20060113547A1
公开(公告)日：2006-06-01
申请号：US11287956
申请日：2005-11-28
申请人： Kwang-Shik Shin
发明人： Kwang-Shik Shin
IPC分类号： H01L31/0312
CPC分类号： H01L27/105 , H01L23/5258 , H01L27/0688 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a semiconductor memory device include forming a plurality of memory cells in a cell region of a semiconductor substrate. An insulating layer is formed on the plurality of memory cells in the cell region and on a peripheral circuit region of the substrate, and a bit line contact plug is formed extending through the insulating layer to the substrate in the cell region. A continuous conductive layer is formed on the insulating layer in the cell region and the peripheral circuit region. The continuous conductive layer is patterned to define a bit line contact pad on the bit line contact plug in the cell region and at least one fuse in the peripheral circuit region, for example, using a same mask pattern. The continuous conductive layer may also be patterned to define a load resistor in the peripheral circuit region. Related devices are also discussed.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的单元区域中形成多个存储单元。在单元区域和基板的外围电路区域的多个存储单元上形成绝缘层，并且形成在单元区域中延伸穿过绝缘层到基板的位线接触插塞。在单元区域和外围电路区域的绝缘层上形成连续的导电层。连续导电层被图案化以在单元区域中的位线接触插塞上限定位线接触焊盘，并且例如使用相同的掩模图案来限定外围电路区域中的至少一个熔丝。连续导电层也可以被图案化以在外围电路区域中限定负载电阻器。还讨论了相关设备。

9. 发明申请

US20050023600A1 NAND-type flash memory devices and methods of fabricating the same 有权
标题翻译： NAND型闪存器件及其制造方法
公开(公告)号：US20050023600A1
公开(公告)日：2005-02-03
申请号：US10921656
申请日：2004-08-19
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115 , H01L27/11524
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要翻译：提供了NAND型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

10. 发明授权

US06797570B2 NAND-type flash memory devices and methods of fabricating the same 有权
标题翻译： NAND型闪存器件及其制造方法
公开(公告)号：US06797570B2
公开(公告)日：2004-09-28
申请号：US10087330
申请日：2002-03-01
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要翻译：提供了NAND型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

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