会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • NAND-type flash memory devices and methods of fabricating the same
    • NAND型闪存器件及其制造方法
    • US06797570B2
    • 2004-09-28
    • US10087330
    • 2002-03-01
    • Kwang-Shik ShinKyu-Charn ParkHeung-Kwun OhSung-Hoi Hur
    • Kwang-Shik ShinKyu-Charn ParkHeung-Kwun OhSung-Hoi Hur
    • H01L21336
    • H01L27/11521H01L27/115
    • NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
    • 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层,它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案,多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。
    • 4. 发明授权
    • Method of fabricating a non-volatile memory device
    • 制造非易失性存储器件的方法
    • US06495467B2
    • 2002-12-17
    • US09994349
    • 2001-11-26
    • Kwang-Shik ShinHee-Hong Yang
    • Kwang-Shik ShinHee-Hong Yang
    • H01L21461
    • H01L27/11521H01L21/28273H01L27/115H01L29/66825
    • A method of fabricating a non-volatile memory device having a U-shaped floating gate is described. This method forms a device isolation layer in a predetermined region of a semiconductor substrate, thereby defining at least one active region. A floating gate pattern covering active regions and having a gap region exposing the device isolation layer therebetween is formed, and an insulation material pattern where the width of a projection is wider than an upper width of the gap region while the projection covers the gap region and is higher then an upper surface of the floating gate pattern is formed. Subsequently, the floating gate pattern is etched using the insulation material pattern, thereby forming a modified floating gate pattern showing a U-shaped cross section on an active region. As a result, a coupling ratio of the non-volatile memory device can be increased.
    • 描述了一种制造具有U形浮动栅极的非易失性存储器件的方法。 该方法在半导体衬底的预定区域中形成器件隔离层,从而限定至少一个有源区。 形成覆盖有源区并具有使其间的器件隔离层露出的间隙区域的浮栅图案,以及当突起覆盖间隙区域时突起的宽度比间隙区域的宽度宽的绝缘材料图案,以及 高于浮栅图案的上表面。 随后,使用绝缘材料图案蚀刻浮置栅极图案,从而在有源区域上形成显示出U形横截面的改进的浮动栅极图案。 结果,可以增加非易失性存储器件的耦合比。
    • 6. 发明申请
    • Methods of fabricating memory devices including fuses and load resistors in a peripheral circuit region
    • 在外围电路区域中制造包括熔丝和负载电阻的存储器件的方法
    • US20060113547A1
    • 2006-06-01
    • US11287956
    • 2005-11-28
    • Kwang-Shik Shin
    • Kwang-Shik Shin
    • H01L31/0312
    • H01L27/105H01L23/5258H01L27/0688H01L27/11519H01L27/11526H01L27/11531H01L27/11551H01L2924/0002H01L2924/00
    • Methods of fabricating a semiconductor memory device include forming a plurality of memory cells in a cell region of a semiconductor substrate. An insulating layer is formed on the plurality of memory cells in the cell region and on a peripheral circuit region of the substrate, and a bit line contact plug is formed extending through the insulating layer to the substrate in the cell region. A continuous conductive layer is formed on the insulating layer in the cell region and the peripheral circuit region. The continuous conductive layer is patterned to define a bit line contact pad on the bit line contact plug in the cell region and at least one fuse in the peripheral circuit region, for example, using a same mask pattern. The continuous conductive layer may also be patterned to define a load resistor in the peripheral circuit region. Related devices are also discussed.
    • 制造半导体存储器件的方法包括在半导体衬底的单元区域中形成多个存储单元。 在单元区域和基板的外围电路区域的多个存储单元上形成绝缘层,并且形成在单元区域中延伸穿过绝缘层到基板的位线接触插塞。 在单元区域和外围电路区域的绝缘层上形成连续的导电层。 连续导电层被图案化以在单元区域中的位线接触插塞上限定位线接触焊盘,并且例如使用相同的掩模图案来限定外围电路区域中的至少一个熔丝。 连续导电层也可以被图案化以在外围电路区域中限定负载电阻器。 还讨论了相关设备。
    • 9. 发明申请
    • EEPROM device having selecting transistors and method of fabricating the same
    • 具有选择晶体管的EEPROM器件及其制造方法
    • US20050012140A1
    • 2005-01-20
    • US10891803
    • 2004-07-14
    • Kwang-Shik ShinHan-Soo KimSung-Hoi Hur
    • Kwang-Shik ShinHan-Soo KimSung-Hoi Hur
    • H01L21/8247G11C11/34H01L27/10H01L27/115H01L29/788H01L29/792
    • H01L27/11524H01L27/115H01L27/11521
    • An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.
    • EEPROM包括用于限定多个有源区的器件隔离层,跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间,并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案,并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。