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    • 3. 发明申请
    • APPARATUS FOR CAPTURING RESULTS OF MEMORY TESTING
    • 用于记录测试结果的装置
    • US20150039950A1
    • 2015-02-05
    • US13955401
    • 2013-07-31
    • International Business Machines Corporation
    • Craig M. MonroeMichael R. OuelletteDouglas E. SpragueMichael A. Ziegerhofer
    • G06F11/27
    • G06F11/27G11C29/44G11C29/56008G11C2029/1208G11C2029/4402G11C2029/5606
    • A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.
    • 一种用于产生联合测试动作组(JTAG)捕捉移位测试数据寄存器的描述文件的方法,用于解释包含在被配置用于测试集成电路存储器的集成电路结构中的存储器的测试结果。 计算机从第一数据文件中提取内置于自检实例中的内存的名称,内置于自测试端口名称的内存和第一存储器的名称。 第一个数据文件控制集成电路组件的分层结构和架构布置。 第一数据文件描述了组件的结构布置,电路径以及组件与集成电路设计的电路之间的连接的分级顺序。 计算机将提取的名称添加到描述文件中,使得描述文件被配置为解释存储器的测试结果。
    • 6. 发明申请
    • STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
    • 突击控制器和主机启动
    • US20140129888A1
    • 2014-05-08
    • US13671605
    • 2012-11-08
    • INTERNATIONAL BUSINESS MACHINES CORPORATION
    • Valerie H. ChickanoskyKevin W. GormanSuzanne GranatoMichael R. OuelletteNancy H. PrattMichael A. Ziegerhofer
    • G01R31/3177
    • G01R31/31724
    • Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.
    • 每个内置自检(BIST)控制器中的每个寄存器包含与至少一个其他BIST控制器特定启动计数不同的BIST控制器特定的起始计数值。 测试控制器同时向所有BIST控制器提供启动命令。 这使得每个BIST控制器使用计数器同时开始BIST控制器特定的开始计数值的倒计时。 每个BIST控制器在倒计时完成时(在相应的BIST控制器中),在对应的BIST域中启动测试过程。 因此,根据不同寄存器中BIST控制器特定的开始计数值的差异,测试过程在至少两个BIST域中的不同时间开始。 此外,在测试过程中,每个交错控制器可以错开交错控制器所连接的相应BIST域内的每个BIST引擎的开始。