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1. 发明申请

US20090111255A1 METHOD FOR FABRICATING TRANSISTOR IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中制作晶体管的方法
公开(公告)号：US20090111255A1
公开(公告)日：2009-04-30
申请号：US12259799
申请日：2008-10-28
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L27/10876
摘要： Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.
摘要翻译：提供了一种在半导体器件中制造晶体管的方法。该方法包括在半导体衬底上形成蚀刻停止层图案; 形成用于覆盖蚀刻停止层图案的半导体层; 形成通过蚀刻所述半导体层图案来暴露所述蚀刻停止层图案的上表面的凹槽; 去除在凹槽中暴露的蚀刻停止层图案; 并形成填充凹槽的栅极。

2. 发明申请

US20090227106A1 METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20090227106A1
公开(公告)日：2009-09-10
申请号：US12164848
申请日：2008-06-30
申请人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
发明人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
IPC分类号： H01L21/283
CPC分类号： H01L21/76837 , H01L21/76826 , H01L21/76828 , H01L27/10885
摘要： Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10−11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.
摘要翻译：这里公开了一种用于制造半导体存储器件的方法，该半导体存储器件在形成用于隔离位线的层间电介质时可以防止位线的氧化。位线形成在形成下面的结构的半导体衬底上。在形成位线的所得结构上形成介电硅层（SOD）层。可在SOD层上进行热处理，其中在约600℃至约1.5℃范围内的温度范围内，水蒸气（H 2 O）与氢气（H 2）的分压比在约1×10-11至约1.55的范围内，约1100°C

3. 发明授权

US07851298B2 Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation 有权
标题翻译：在半导体器件中制造晶体管的方法，其利用蚀刻停止层图案作为栅电极形成的虚设图案
公开(公告)号：US07851298B2
公开(公告)日：2010-12-14
申请号：US12259799
申请日：2008-10-28
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L27/10876
摘要： Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.
摘要翻译：提供了一种在半导体器件中制造晶体管的方法。该方法包括在半导体衬底上形成蚀刻停止层图案; 形成用于覆盖蚀刻停止层图案的半导体层; 形成通过蚀刻所述半导体层图案来暴露所述蚀刻停止层图案的上表面的凹槽; 去除在凹槽中暴露的蚀刻停止层图案; 并形成填充凹槽的栅极。

4. 发明授权

US07589012B1 Method for fabricating semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US07589012B1
公开(公告)日：2009-09-15
申请号：US12164848
申请日：2008-06-30
申请人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
发明人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76837 , H01L21/76826 , H01L21/76828 , H01L27/10885
摘要： Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10−11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.
摘要翻译：这里公开了一种用于制造半导体存储器件的方法，该半导体存储器件在形成用于隔离位线的层间电介质时可以防止位线的氧化。位线形成在形成下面的结构的半导体衬底上。在形成位线的所得结构上形成介电硅层（SOD）层。可在SOD层上进行热处理，其中在约600℃至约1.5℃范围内的温度范围内，水蒸气（H 2 O）与氢气（H 2）的分压比在约1×10-11至约1.55的范围内，约1100°C

5. 发明申请

US20090004816A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090004816A1
公开(公告)日：2009-01-01
申请号：US11949960
申请日：2007-12-04
申请人： An Bae Lee , Yong Seok Eun , Su Ho Kim , Hye Jin Seo
发明人： An Bae Lee , Yong Seok Eun , Su Ho Kim , Hye Jin Seo
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method of forming an isolation layer in a semiconductor device using rapid vapor deposition to fill in a trench of the semiconductor device comprises forming a hydrophilic layer on the trench and forming a hydrophobic layer on a region other than the trench, and selectively forming a buried insulating layer in the trench using a catalytic reaction of the hydrophilic layer.
摘要翻译：在使用快速气相沉积以填充半导体器件的沟槽的半导体器件中形成隔离层的方法包括在沟槽上形成亲水层并在沟槽以外的区域上形成疏水层，并且选择性地形成掩埋使用亲水层的催化反应在沟槽中的绝缘层。

6. 发明申请

US20080160716A1 METHOD FOR FABRICATING AN ISOLATION LAYER IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中制造隔离层的方法
公开(公告)号：US20080160716A1
公开(公告)日：2008-07-03
申请号：US11770522
申请日：2007-06-28
申请人： Hye Jin Seo , Eun A. Lee , An Bae Lee
发明人： Hye Jin Seo , Eun A. Lee , An Bae Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76229
摘要： A method for forming an isolation layer in a semiconductor device includes forming a trench inside a semiconductor substrate, forming a fluid insulating layer over the semiconductor substrate, thereby filling the trench with the fluid insulating layer, curing the semiconductor substrate by plasma oxidation to densify the fluid insulating layer, and planarizing the fluid insulating layer to form an isolation layer.
摘要翻译：在半导体器件中形成隔离层的方法包括在半导体衬底内形成沟槽，在半导体衬底上形成流体绝缘层，从而用流体绝缘层填充沟槽，通过等离子体氧化固化半导体衬底，流体绝缘层，并且平坦化流体绝缘层以形成隔离层。

7. 发明申请

US20130102120A1 METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造相变存储器件和半导体器件的方法
公开(公告)号：US20130102120A1
公开(公告)日：2013-04-25
申请号：US13339891
申请日：2011-12-29
申请人： Hye Jin Seo , Keum Bum Lee
发明人： Hye Jin Seo , Keum Bum Lee
IPC分类号： H01L21/62
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/126 , H01L45/1608 , H01L45/1683
摘要： Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.
摘要翻译：提供了制造相变存储器件和半导体器件的方法。制造相变存储器件的方法包括在半导体衬底上形成开关器件层，欧姆接触层和硬掩模层，图案化硬掩模层以形成硬掩模图案，蚀刻欧姆层和使用硬掩模图案形成包括欧姆接触图案，开关器件图案和硬掩模图案的图案结构的切换层，选择性地氧化图案结构的表面，形成绝缘层以埋藏图案结构，并且选择性地除去其氧化表面以外的硬掩模图案以形成接触孔。

8. 发明授权

US07893421B2 Phase change memory device capable of satisfying reset current characteristic and contact resistance characteristic 有权
标题翻译：相变存储器件能够满足复位电流特性和接触电阻特性
公开(公告)号：US07893421B2
公开(公告)日：2011-02-22
申请号：US12482607
申请日：2009-06-11
申请人： Keum Bum Lee , Hye Jin Seo , Hyung Suk Lee
发明人： Keum Bum Lee , Hye Jin Seo , Hyung Suk Lee
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/126 , H01L45/16
摘要： A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.
摘要翻译：提出了一种相变存储器件，其具有下电极接触，其具有从下电阻下端到较高电阻上端的梯度电阻分布。相变存储器件包括半导体衬底，下电极接触和相变图案。半导体衬底具有开关器件。下部电极接触形成在开关器件上，并且具有从下部电极接触件的下部向上部逐渐增加的电阻率。相变图案层形成在下电极触点上。

9. 发明授权

US08609503B2 Phase change memory device and fabrication method thereof 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08609503B2
公开(公告)日：2013-12-17
申请号：US13357882
申请日：2012-01-25
申请人： Keum Bum Lee , Su Jin Chae , Hye Jin Seo
发明人： Keum Bum Lee , Su Jin Chae , Hye Jin Seo
IPC分类号： H01L21/8239
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.
摘要翻译：一种相变存储器件的制造，其包括开关器件，与开关器件接触的底部电极触点和形成在底部电极触点上的多孔间隔物。形成的底部电极接触使形成有开关器件的半导体衬底上的开关器件暴露，通过使用具有不同原子尺寸的材料的绝缘化合物，在包括底部电极接触的半导体衬底的合成结构上形成绝缘层，以及通过选择性地蚀刻绝缘层，在底部电极接触孔内形成绝缘间隔物。

10. 发明申请

US20080081430A1 Method For Fabricating Capacitor In Semiconductor Device 失效
标题翻译：半导体器件制造电容器的方法
公开(公告)号：US20080081430A1
公开(公告)日：2008-04-03
申请号：US11758507
申请日：2007-06-05
申请人： Cheol Hwan Park , Dong-Su Park , Eun A. Lee , Hye Jin Seo
发明人： Cheol Hwan Park , Dong-Su Park , Eun A. Lee , Hye Jin Seo
IPC分类号： H01L21/24
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.
摘要翻译：公开了一种在半导体器件中形成电容器的方法。该方法包括在半导体衬底上形成存储节点电极，在存储节点电极上形成具有高介电常数的电介质层，在电介质层上沉积平板电极，从而形成副产物杂质，除去副产物杂质通过在半导体衬底上引入含氢（H）原子的气体，同时在平板电极上沉积覆盖层而残留在平板电极上。

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