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1. 发明授权

US08283958B2 Delay-locked loop and electronic device including the same 有权
标题翻译：延迟锁定环路和电子设备包括相同的
公开(公告)号：US08283958B2
公开(公告)日：2012-10-09
申请号：US12659010
申请日：2010-02-23
申请人： Jong-Ryun Choi , Dong Hwan Lee , Su Ho Kim , Won Lee , Alex Joo , Ji Hun Oh
发明人： Jong-Ryun Choi , Dong Hwan Lee , Su Ho Kim , Won Lee , Alex Joo , Ji Hun Oh
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/0818 , H03L7/10
摘要： A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
摘要翻译：提供延迟锁定环。延迟锁定环控制在锁定操作期间延迟输入时钟的相位的延迟单元的数量，并且在锁定操作完成之后控制多个延迟单元中的至少一个延迟单元的相位延迟值。

2. 发明授权

US07994835B2 Duty control circuit and semiconductor device having the same 有权
标题翻译：占空比控制电路和具有相同功能的半导体器件
公开(公告)号：US07994835B2
公开(公告)日：2011-08-09
申请号：US12585680
申请日：2009-09-22
申请人： Kwan-yeob Chae , Su-ho Kim , Won Lee , Sang-hoon Joo , Dharmendra Pandit , Jong-ryun Choi
发明人： Kwan-yeob Chae , Su-ho Kim , Won Lee , Sang-hoon Joo , Dharmendra Pandit , Jong-ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058
摘要： A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.
摘要翻译：一种占空比控制电路，包括连接到第一节点和第二节点的时钟输入单元，时钟输入单元通过第一节点接收输入时钟信号，并将第二节点的电压改变为第一电压电平和第二节点之一响应于输入时钟信号的相应低和高逻辑电平的电压电平，连接到第二节点的转换控制器，所述转换控制器包括由相应控制信号控制的一个或多个开关，所述一个或多个开关提供第一电压电平和第二电压电平响应于控制信号，使得第二节点处的信号的转换速率改变;以及时钟输出单元，时钟输出单元输出具有占空比的输出时钟信号不一样。

3. 发明授权

US07990195B2 Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes 有权
标题翻译：具有对温度变化相对不敏感的短锁定时间的占空比校正电路
公开(公告)号：US07990195B2
公开(公告)日：2011-08-02
申请号：US12603717
申请日：2009-10-22
申请人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
发明人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
摘要翻译：占空比校正电路包括占空比校正部分，其被配置为输出通过校正输入信号的占空比获得的校正信号，并输出通过延迟校正信号而获得的延迟信号;互补部分，被配置为输出作为所述延迟信号的互补的互补信号，以及相位插值器，被配置为相互插补所述互补信号和所述校正信号。

4. 发明授权

US07723189B2 Method for manufacturing semiconductor device having recess gate 失效
标题翻译：具有凹槽的半导体器件的制造方法
公开(公告)号：US07723189B2
公开(公告)日：2010-05-25
申请号：US11618565
申请日：2006-12-29
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L29/66583
摘要： A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.
摘要翻译：一种用于制造具有凹槽的半导体器件的方法包括在半导体衬底上形成蚀刻停止膜; 通过图案化所述蚀刻停止膜形成选择性地暴露所述半导体衬底的蚀刻停止膜图案; 在半导体衬底上形成半导体层; 在半导体衬底上形成用于形成用于凹槽的沟槽的暴露区域的硬掩模膜图案; 使用硬掩模膜图案作为掩模去除半导体层，直到蚀刻停止膜图案被曝光; 通过从半导体衬底去除蚀刻停止膜图案来形成凹槽的沟槽; 以及形成栅极堆叠，每个栅极堆叠形成在用于凹槽的相应的一个沟槽中。

5. 发明申请

US20080277375A1 Method for manufacturing flexible display substrate and flexible display device 有权
标题翻译：制造柔性显示基板和柔性显示装置的方法
公开(公告)号：US20080277375A1
公开(公告)日：2008-11-13
申请号：US11980650
申请日：2007-10-31
申请人： Seung Han Paek , Kyoung Mook Lee , Sung Hwan Kim , Su Ho Kim
发明人： Seung Han Paek , Kyoung Mook Lee , Sung Hwan Kim , Su Ho Kim
IPC分类号： H01B13/00
CPC分类号： G02F1/167 , G02F1/133305 , G02F1/133351
摘要： A method for manufacturing a flexible electrophoretic display device, including: providing a metal mother substrate having a first thickness, including a unit display panel region and a non-display region adjacent the unit display panel region; forming a display element in the unit display panel region; forming a groove in the non-display region of the mother substrate; cutting the mother substrate along the groove to separate the unit display panel region from the mother substrate; thinning the substrate of the separated unit display panel region; and forming an electrophoretic film on the unit display panel region.
摘要翻译：一种制造柔性电泳显示装置的方法，包括：提供具有第一厚度的金属母基板，包括单元显示面板区域和邻近单元显示面板区域的非显示区域; 在所述单元显示面板区域中形成显示元件; 在母基板的非显示区域中形成凹槽; 沿着凹槽切割母体衬底以将单元显示面板区域与母体衬底分离; 使分离的单元显示面板区域的基板变薄; 并在单位显示面板区域上形成电泳膜。

6. 发明申请

US20050118786A1 Method for forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20050118786A1
公开(公告)日：2005-06-02
申请号：US10889480
申请日：2004-07-12
申请人： Su Ho Kim , Yun Hyuck Ji
发明人： Su Ho Kim , Yun Hyuck Ji
IPC分类号： H01L21/76 , H01L21/762 , H01L29/80 , H01L31/112
CPC分类号： H01L21/76232
摘要： Disclosed is a method for forming an isolation layer of a semiconductor device. The method includes the steps of providing a semiconductor substrate having a predetermined isolation region, sequentially forming a pad oxide layer and a pad nitride layer exposing the predetermined isolation region on the semiconductor substrate, forming a trench through etching the semiconductor substrate by a predetermined thickness using the pad nitride layer as a mask, forming a wall oxide layer at a side wall of the trench, sequentially forming a nitride layer and an oxide layer on a trench structure including the wall oxide layer, forming an Al2O3 layer on an entire surface of a resultant structure, planarizing the Al2O3 layer through polishing the Al2O3 layer, and forming the isolation layer by removing the pad nitride layer.
摘要翻译：公开了一种形成半导体器件隔离层的方法。该方法包括以下步骤：提供具有预定隔离区域的半导体衬底，顺序地形成衬垫氧化物层和暴露半导体衬底上的预定隔离区域的衬垫氮化物层，通过使用衬垫氮化物层作为掩模，在沟槽的侧壁处形成壁氧化物层，在包括壁氧化物层的沟槽结构上依次形成氮化物层和氧化物层，形成Al 2 在所得结构的整个表面上形成O 3层，通过抛光Al 2 O 3层平坦化Al 2 O 3层，以及通过去除衬垫氮化物层形成隔离层。

7. 发明授权

US08349194B2 Method for manufacturing flexible display substrate and flexible display device 有权
标题翻译：制造柔性显示基板和柔性显示装置的方法
公开(公告)号：US08349194B2
公开(公告)日：2013-01-08
申请号：US11980650
申请日：2007-10-31
申请人： Seung Han Paek , Kyoung Mook Lee , Sung Hwan Kim , Su Ho Kim
发明人： Seung Han Paek , Kyoung Mook Lee , Sung Hwan Kim , Su Ho Kim
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： G02F1/167 , G02F1/133305 , G02F1/133351
摘要： A method for manufacturing a flexible electrophoretic display device, including: providing a metal mother substrate having a first thickness, including a unit display panel region and a non-display region adjacent the unit display panel region; forming a display element in the unit display panel region; forming a groove in the non-display region of the mother substrate; cutting the mother substrate along the groove to separate the unit display panel region from the mother substrate; thinning the substrate of the separated unit display panel region; and forming an electrophoretic ink film on the unit display panel region.
摘要翻译：一种制造柔性电泳显示装置的方法，包括：提供具有第一厚度的金属母基板，包括单元显示面板区域和邻近单元显示面板区域的非显示区域; 在所述单元显示面板区域中形成显示元件; 在母基板的非显示区域中形成凹槽; 沿着凹槽切割母体衬底以将单元显示面板区域与母体衬底分离; 使分离的单元显示面板区域的基板变薄; 以及在单位显示面板区域上形成电泳墨膜。

8. 发明申请

US20100097112A1 DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES 有权
标题翻译：具有相对温度变化敏感的短暂锁定时间的周期校正电路
公开(公告)号：US20100097112A1
公开(公告)日：2010-04-22
申请号：US12603717
申请日：2009-10-22
申请人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
发明人： Harmendra Panditd , Su Ho Kim , Won Lee , Alex Joo , Kwan Yeob Chae , Jong-Ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
摘要翻译：占空比校正电路包括占空比校正部分，其被配置为输出通过校正输入信号的占空比获得的校正信号，并输出通过延迟校正信号而获得的延迟信号;互补部分，被配置为输出作为所述延迟信号的互补的互补信号，以及相位插值器，被配置为相互插补所述互补信号和所述校正信号。

9. 发明申请

US20090227106A1 METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20090227106A1
公开(公告)日：2009-09-10
申请号：US12164848
申请日：2008-06-30
申请人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
发明人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
IPC分类号： H01L21/283
CPC分类号： H01L21/76837 , H01L21/76826 , H01L21/76828 , H01L27/10885
摘要： Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10−11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.
摘要翻译：这里公开了一种用于制造半导体存储器件的方法，该半导体存储器件在形成用于隔离位线的层间电介质时可以防止位线的氧化。位线形成在形成下面的结构的半导体衬底上。在形成位线的所得结构上形成介电硅层（SOD）层。可在SOD层上进行热处理，其中在约600℃至约1.5℃范围内的温度范围内，水蒸气（H 2 O）与氢气（H 2）的分压比在约1×10-11至约1.55的范围内，约1100°C

10. 发明申请

US20050136575A1 Method for forming gate of semiconductor device 审中-公开
标题翻译：半导体器件栅极形成方法
公开(公告)号：US20050136575A1
公开(公告)日：2005-06-23
申请号：US10889483
申请日：2004-07-12
申请人： Su Ho Kim , Sang Ho Woo , Yong Seok Eun
发明人： Su Ho Kim , Sang Ho Woo , Yong Seok Eun
IPC分类号： H01L21/336 , H01L21/00 , H01L21/28 , H01L21/8234 , H01L21/8242 , H01L21/84
CPC分类号： H01L21/28176 , H01L21/28061 , H01L21/823462
摘要： Disclosed is a method for forming a gate of a semiconductor device. The method includes the steps of forming a first oxide layer on a substrate divided into a cell area and a peripheral circuit area, forming a photoresist film pattern on a cell area, thereby exposing a surface of the first oxide layer, removing the exposed first oxide layer formed in the peripheral circuit area, and then, removing the photoresist film, forming a second oxide layer on a surface of the silicon substrate, in which the first oxide layer of the peripheral circuit area is removed, and on a first gate oxide layer of the cell area, forming a poly silicon layer on the second oxide layer, forming a tungsten silicide layer on the poly silicon layer, and sequentially patterning the tungsten silicide layer, the poly silicon layer, the second oxide layer, and the first oxide layer.
摘要翻译：公开了一种形成半导体器件的栅极的方法。该方法包括以下步骤：在分为单元区域和外围电路区域的基板上形成第一氧化物层，在单元区域形成光致抗蚀剂图案，从而暴露第一氧化物层的表面，去除暴露的第一氧化物在所述外围电路区域中形成的层，然后除去所述光致抗蚀剂膜，在除去所述外围电路区域的所述第一氧化物层的所述硅衬底的表面上形成第二氧化物层，并且在第一栅极氧化物层在所述第二氧化物层上形成多晶硅层，在所述多晶硅层上形成硅化钨层，并顺序构图所述硅化钨层，所述多晶硅层，所述第二氧化物层和所述第一氧化物层。

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