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1. 发明申请

US20130102120A1 METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造相变存储器件和半导体器件的方法
公开(公告)号：US20130102120A1
公开(公告)日：2013-04-25
申请号：US13339891
申请日：2011-12-29
申请人： Hye Jin Seo , Keum Bum Lee
发明人： Hye Jin Seo , Keum Bum Lee
IPC分类号： H01L21/62
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/126 , H01L45/1608 , H01L45/1683
摘要： Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.
摘要翻译：提供了制造相变存储器件和半导体器件的方法。制造相变存储器件的方法包括在半导体衬底上形成开关器件层，欧姆接触层和硬掩模层，图案化硬掩模层以形成硬掩模图案，蚀刻欧姆层和使用硬掩模图案形成包括欧姆接触图案，开关器件图案和硬掩模图案的图案结构的切换层，选择性地氧化图案结构的表面，形成绝缘层以埋藏图案结构，并且选择性地除去其氧化表面以外的硬掩模图案以形成接触孔。

2. 发明授权

US07893421B2 Phase change memory device capable of satisfying reset current characteristic and contact resistance characteristic 有权
标题翻译：相变存储器件能够满足复位电流特性和接触电阻特性
公开(公告)号：US07893421B2
公开(公告)日：2011-02-22
申请号：US12482607
申请日：2009-06-11
申请人： Keum Bum Lee , Hye Jin Seo , Hyung Suk Lee
发明人： Keum Bum Lee , Hye Jin Seo , Hyung Suk Lee
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/126 , H01L45/16
摘要： A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.
摘要翻译：提出了一种相变存储器件，其具有下电极接触，其具有从下电阻下端到较高电阻上端的梯度电阻分布。相变存储器件包括半导体衬底，下电极接触和相变图案。半导体衬底具有开关器件。下部电极接触形成在开关器件上，并且具有从下部电极接触件的下部向上部逐渐增加的电阻率。相变图案层形成在下电极触点上。

3. 发明授权

US08546177B2 Methods of manufacturing phase-change memory device and semiconductor device 有权
标题翻译：制造相变存储器件和半导体器件的方法
公开(公告)号：US08546177B2
公开(公告)日：2013-10-01
申请号：US13339891
申请日：2011-12-29
申请人： Hye Jin Seo , Keum Bum Lee
发明人： Hye Jin Seo , Keum Bum Lee
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/126 , H01L45/1608 , H01L45/1683
摘要： Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.
摘要翻译：提供了制造相变存储器件和半导体器件的方法。制造相变存储器件的方法包括在半导体衬底上形成开关器件层，欧姆接触层和硬掩模层，图案化硬掩模层以形成硬掩模图案，蚀刻欧姆层和使用硬掩模图案形成包括欧姆接触图案，开关器件图案和硬掩模图案的图案结构的切换层，选择性地氧化图案结构的表面，形成绝缘层以埋藏图案结构，并且选择性地除去其氧化表面以外的硬掩模图案以形成接触孔。

4. 发明授权

US08609503B2 Phase change memory device and fabrication method thereof 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08609503B2
公开(公告)日：2013-12-17
申请号：US13357882
申请日：2012-01-25
申请人： Keum Bum Lee , Su Jin Chae , Hye Jin Seo
发明人： Keum Bum Lee , Su Jin Chae , Hye Jin Seo
IPC分类号： H01L21/8239
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.
摘要翻译：一种相变存储器件的制造，其包括开关器件，与开关器件接触的底部电极触点和形成在底部电极触点上的多孔间隔物。形成的底部电极接触使形成有开关器件的半导体衬底上的开关器件暴露，通过使用具有不同原子尺寸的材料的绝缘化合物，在包括底部电极接触的半导体衬底的合成结构上形成绝缘层，以及通过选择性地蚀刻绝缘层，在底部电极接触孔内形成绝缘间隔物。

5. 发明授权

US09406871B2 Magnetoresistive element and method of manufacturing the same 有权
公开(公告)号：US09406871B2
公开(公告)日：2016-08-02
申请号：US14807267
申请日：2015-07-23
申请人： Masahiko Nakayama , Masatoshi Yoshikawa , Tadashi Kai , Yutaka Hashimoto , Masaru Toko , Hiroaki Yoda , Jae Geun Oh , Keum Bum Lee , Choon Kun Ryu , Hyung Suk Lee , Sook Joo Kim
发明人： Masahiko Nakayama , Masatoshi Yoshikawa , Tadashi Kai , Yutaka Hashimoto , Masaru Toko , Hiroaki Yoda , Jae Geun Oh , Keum Bum Lee , Choon Kun Ryu , Hyung Suk Lee , Sook Joo Kim
IPC分类号： H01L43/00 , H01L43/02 , H01L27/22 , H01L43/08 , H01L43/12 , H01L43/10
CPC分类号： H01L43/02 , H01L27/222 , H01L27/224 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12
摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

6. 发明授权

US09123879B2 Magnetoresistive element and method of manufacturing the same 有权
标题翻译：磁阻元件及其制造方法
公开(公告)号：US09123879B2
公开(公告)日：2015-09-01
申请号：US14202802
申请日：2014-03-10
申请人： Masahiko Nakayama , Masatoshi Yoshikawa , Tadashi Kai , Yutaka Hashimoto , Masaru Toko , Hiroaki Yoda , Jae Geun Oh , Keum Bum Lee , Choon Kun Ryu , Hyung Suk Lee , Sook Joo Kim
发明人： Masahiko Nakayama , Masatoshi Yoshikawa , Tadashi Kai , Yutaka Hashimoto , Masaru Toko , Hiroaki Yoda , Jae Geun Oh , Keum Bum Lee , Choon Kun Ryu , Hyung Suk Lee , Sook Joo Kim
IPC分类号： H01L27/00 , H01L43/02 , H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： H01L43/02 , H01L27/222 , H01L27/224 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12
摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.
摘要翻译：根据一个实施例，公开了一种磁阻元件。磁阻元件包括参考层，隧道势垒层，存储层。存储层包括第一区域和设置在第一区域外部以围绕第一区域的第二区域，第二区域包括包含在第一区域中的元素，而另一个元素不同于元件。磁阻元件进一步包括盖层，该盖层包括第三区域和设置在第三区域外部以包围第三区域的第四区域，第四区域包括包括在第三区域中的元件和另一元件。

7. 发明申请

US20090321705A1 PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090321705A1
公开(公告)日：2009-12-31
申请号：US12256385
申请日：2008-10-22
申请人： Min Yong Lee , Su Jin Chae , Keum Bum Lee , Dong Ryeol Lee , Hyung Suk Lee
发明人： Min Yong Lee , Su Jin Chae , Keum Bum Lee , Dong Ryeol Lee , Hyung Suk Lee
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/06 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern.
摘要翻译：相变存储器件包括半导体衬底，形成在半导体衬底上的第一导电图案，与第一导电图案的上表面接触并具有小于第一导电图案的直径的直径的第二导电图案，以及相位改变与第二导电图案接触的材料层。

8. 发明申请

US20090045389A1 PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090045389A1
公开(公告)日：2009-02-19
申请号：US12169612
申请日：2008-07-08
申请人： Yong Seok Eun , Su Jin Chae , Keum Bum Lee , Heon Yong Chang , Min Yong Lee
发明人： Yong Seok Eun , Su Jin Chae , Keum Bum Lee , Heon Yong Chang , Min Yong Lee
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/1233 , G11C13/0004 , H01L45/06 , H01L45/1253 , H01L45/16
摘要： A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.
摘要翻译：相变存储装置及其制造方法。该方法包括以下步骤：通过去除绝缘层的一部分来暴露底部电极，在其上依次形成底部电极和绝缘层的半导体衬底上限定底部电极接触孔; 在底部电极接触孔的内侧壁上形成非晶硅间隔物; 以及在底部电极接触孔中形成底部电极接触。

9. 发明申请

US20070264770A1 CAPACITOR FORMING METHOD 审中-公开
标题翻译：电容成型方法
公开(公告)号：US20070264770A1
公开(公告)日：2007-11-15
申请号：US11618796
申请日：2006-12-30
申请人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
发明人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
IPC分类号： H01L21/8242 , H01L29/92
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/02189 , H01L21/022 , H01L21/0228 , H01L21/0234 , H01L27/10852 , H01L28/91
摘要： A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.
摘要翻译：形成电容器的方法包括在半导体衬底上形成凹模。存储节点形成在凹模上。包含氧化锆（ZrO 2）层的电介质层在第一温度下沉积在存储节点上。在包括自由基的气氛中，在高于第一温度的第二温度下进行介电层上的自由基堆积处理，以诱导电介质层的结晶。在该电介质层上形成一个平板节点。

10. 发明申请

US20080070398A1 Method For Fabricating Semiconductor Device Having Metal Fuse 审中-公开
标题翻译：制造具有金属保险丝的半导体器件的方法
公开(公告)号：US20080070398A1
公开(公告)日：2008-03-20
申请号：US11758512
申请日：2007-06-05
申请人： Dong Su Park , Ho Jin Cho , Keum Bum Lee , Su Jin Chae , Cheol-Hwan Park
发明人： Dong Su Park , Ho Jin Cho , Keum Bum Lee , Su Jin Chae , Cheol-Hwan Park
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection. The method further includes forming an inter-metal dielectric layer on the first metal interconnection and the fuse, forming a second metal interconnection on the inter-metal dielectric layer, forming a passivation layer on the second metal interconnection, and forming a fuse box in the passivation layer.
摘要翻译：这里公开了一种制造具有金属保险丝的半导体器件的方法。该方法包括在半导体衬底上形成平板电极，在平板电极上形成层间绝缘层，从底部依次形成含有硅或铝的阻挡金属层，第一金属层和含有硅或铝的抗反射层，顶层在层间绝缘层上。该方法还包括图案化抗反射层，第一金属层和阻挡金属层以形成第一金属互连。该方法还包括形成具有与第一金属互连相同的材料和结构的熔丝，同时形成第一金属互连。该方法还包括在第一金属互连和熔丝上形成金属间电介质层，在金属间绝缘层上形成第二金属互连，在第二金属互连上形成钝化层，并在第钝化层。

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