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1. 发明授权

US07638407B2 Method for forming capacitor of semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US07638407B2
公开(公告)日：2009-12-29
申请号：US12265759
申请日：2008-11-06
申请人： Cheol Hwan Park , Ho Jin Cho , Jae Soo Kim , Dong Kyun Lee
发明人： Cheol Hwan Park , Ho Jin Cho , Jae Soo Kim , Dong Kyun Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/91
摘要： Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.
摘要翻译：形成半导体器件的电容器包括在半导体衬底上形成具有孔的层间电介质。然后在孔的表面和层间电介质的上表面上形成导电层。通过使形成有导电层的半导体衬底的硅源气体流动而形成含硅导电层，使得硅原子能够渗透到导电层中。含硅导电层防止蚀刻剂渗透到含硅导电层之下的层间电介质。

2. 发明授权

US07576383B2 Capacitor having tapered cylindrical storage node and method for manufacturing the same 有权
标题翻译：具有锥形圆柱形存储节点的电容器及其制造方法
公开(公告)号：US07576383B2
公开(公告)日：2009-08-18
申请号：US11779093
申请日：2007-07-17
申请人： Ho Jin Cho , Cheol Hwan Park , Jae Soo Kim , Dong Kyun Lee
发明人： Ho Jin Cho , Cheol Hwan Park , Jae Soo Kim , Dong Kyun Lee
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/91
摘要： A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.
摘要翻译：通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。在包括孔的模具绝缘层上沉积渐缩层。锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。在存储节点上形成介电层和板状节点。

3. 发明授权

US07084072B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07084072B2
公开(公告)日：2006-08-01
申请号：US10874983
申请日：2004-06-23
申请人： Cheol Hwan Park , Sang Ho Woo , Chang Rock Song , Dong Su Park , Tae Hyeok Lee
发明人： Cheol Hwan Park , Sang Ho Woo , Chang Rock Song , Dong Su Park , Tae Hyeok Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/28141 , H01L21/3144 , H01L21/3185 , H01L27/1052 , H01L27/10873
摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming a gate in a cell region and a peripheral region of a substrate, depositing a buffer oxide layer on the gate and the substrate, annealing a resultant structure of the substrate, depositing a nitride spacer layer on the buffer oxide layer, depositing an oxide spacer layer on the nitride spacer layer, forming an oxide spacer at the peripheral region of the substrate, and removing the oxide spacer layer remaining in the cell region. The annealing step is additionally carried out after depositing the buffer oxide layer so as to improve the interfacial surface characteristic and film quality, so that oxide etchant is prevented from penetrating into the silicon substrate during the wet dip process. Unnecessary voids are prevented from being created in the silicon substrate.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：在衬底的单元区域和外围区域中形成栅极，在栅极和衬底上沉积缓冲氧化物层，退火所得衬底的结构，在缓冲氧化物上沉积氮化物间隔层在所述氮化物间隔层上沉积氧化物间隔层，在所述衬底的周围区域形成氧化物间隔物，以及去除所述电池区域中剩余的氧化物间隔层。在沉积缓冲氧化物层之后另外进行退火步骤，以改善界面表面特性和膜质量，从而防止在湿法浸渍过程中氧化物蚀刻剂渗入硅衬底。防止在硅衬底中产生不必要的空隙。

4. 发明授权

US06964930B2 Method of fabricating dielectric layer 有权
标题翻译：介电层制作方法
公开(公告)号：US06964930B2
公开(公告)日：2005-11-15
申请号：US10739620
申请日：2003-12-18
申请人： Dong Su Park , Tae Hyeok Lee , Chang Rock Song , Cheol Hwan Park
发明人： Dong Su Park , Tae Hyeok Lee , Chang Rock Song , Cheol Hwan Park
IPC分类号： H01L21/318 , C23C16/02 , C23C16/34 , C23C16/56 , H01L21/20 , H01L21/306 , H01L21/314 , H01L29/51 , H01L29/78 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02247 , C23C16/0227 , C23C16/345 , C23C16/56 , H01L21/02052 , H01L21/022 , H01L21/0223 , H01L21/02255 , H01L21/02271 , H01L21/3144 , H01L21/3145 , H01L29/513 , H01L29/518 , Y10S438/954
摘要： In fabricating a dielectric layer, a semiconductor substrate which has been washed is provided. A first nitride film is formed by loading the substrate in a first furnace and subjecting the substrate to a first nitride treatment. A first oxide film is formed by unloading the substrate having the first nitride film out of the first furnace and subjecting the substrate to a first nitride treatment by introducing air while the substrate is unloaded. A second nitride film is formed by loading the substrate having the first oxide film in a second furnace and subjecting the substrate to a second nitride treatment. A second oxide film is formed by subjecting the top surface of the second nitride film to a second oxide treatment.
摘要翻译：在制造电介质层时，提供已洗涤的半导体衬底。第一氮化物膜通过将基板装载在第一炉中并对基板进行第一氮化物处理而形成。通过将具有第一氮化物膜的衬底从第一炉中卸出并通过在衬底卸载的同时引入空气对衬底进行第一氮化物处理来形成第一氧化物膜。通过将具有第一氧化物膜的衬底装载在第二炉中并对衬底进行第二氮化物处理来形成第二氮化物膜。通过对第二氮化物膜的顶表面进行第二氧化物处理来形成第二氧化物膜。

5. 发明授权

US06913963B2 Method for fabricating capacitor in semiconductor device 失效
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US06913963B2
公开(公告)日：2005-07-05
申请号：US10331422
申请日：2002-12-30
申请人： Tae Hyeok Lee , Cheol Hwan Park , Dong Su Park , Sang Ho Woo
发明人： Tae Hyeok Lee , Cheol Hwan Park , Dong Su Park , Sang Ho Woo
IPC分类号： C23C16/42 , H01L21/02 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/318 , H01L21/82 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/04 , H01L27/108
CPC分类号： H01L28/40 , H01L21/0214 , H01L21/0217 , H01L21/0228 , H01L21/3185
摘要： A method for fabricating a capacitor for a semiconductor device is disclosed, which comprises the steps of: forming a storage node electrode on a semiconductor wafer, forming a dielectric layer made of a cyclic silicon nitride layer on the surface of the storage node electrode, and forming an upper electrode on the dielectric layer; lowering the thickness Teff of the dielectric layer and improving leakage current characteristics through use of a cyclic Si3N4 or a cyclic SiOxNy (wherein x falls between 0.1 and 0.9 and y falls between 0.1 and 2), having a large oxidation resistance and high dielectric ratio, as a dielectric.
摘要翻译：公开了一种制造用于半导体器件的电容器的方法，其包括以下步骤：在半导体晶片上形成存储节点电极，在存储节点电极的表面上形成由环状氮化硅层制成的电介质层，以及在所述电介质层上形成上电极; 降低电介质层的厚度T eff，并且通过使用环状Si 3 N 4 N或环状SiO

6. 发明授权

US06884678B2 Method for forming capacitor of semiconductor device 失效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：US06884678B2
公开(公告)日：2005-04-26
申请号：US10608429
申请日：2003-06-30
申请人： Dong Su Park , Tae Hyeok Lee , Cheol Hwan Park
发明人： Dong Su Park , Tae Hyeok Lee , Cheol Hwan Park
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/318
CPC分类号： H01L21/3185 , H01L21/0217 , H01L21/02183 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L27/10852 , H01L28/91
摘要： A method for forming of a capacitor wherein an etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film is disclosed. The method comprises the steps of: forming an etching barrier layer on an interlayer insulating film having a storage electrode contact plug therein, the etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film; forming an oxide film on the etching barrier layer; selectively etching the oxide film and the etching barrier layer to form an opening exposing the storage electrode contact plug; depositing a storage electrode layer on the bottom and the inner walls of the opening; and removing the oxide film, whereby forming a storage electrode.
摘要翻译：一种形成电容器的方法，其中公开了包括氮化物膜和钽氧化物膜的叠层结构的蚀刻阻挡层。该方法包括以下步骤：在其上具有存储电极接触插塞的层间绝缘膜上形成蚀刻阻挡层，所述蚀刻阻挡层包括氮化物膜和氧化钽膜的堆叠结构; 在蚀刻阻挡层上形成氧化膜; 选择性地蚀刻氧化膜和蚀刻阻挡层以形成暴露存储电极接触插塞的开口; 在开口的底部和内壁上沉积存储电极层; 除去氧化膜，由此形成存储电极。

7. 发明授权

US09142634B2 Versatile spin-polarized electron source 有权
标题翻译：多功能自旋极化电子源
公开(公告)号：US09142634B2
公开(公告)日：2015-09-22
申请号：US14185651
申请日：2014-02-20
申请人： Chris Jozwiak , Cheol-Hwan Park , Kenneth Gotlieb , Steven G Louie , Zahid Hussain , Alessandra Lanzara
发明人： Chris Jozwiak , Cheol-Hwan Park , Kenneth Gotlieb , Steven G Louie , Zahid Hussain , Alessandra Lanzara
IPC分类号： H01L21/00 , H01L29/66
CPC分类号： H01L29/66007 , G21K1/16 , H01J1/34 , H01L29/66984
摘要： One or more embodiments relate generally to the field of photoelectron spin and, more specifically, to a method and system for creating a controllable spin-polarized electron source. One preferred embodiment of the invention generally comprises: method for creating a controllable spin-polarized electron source comprising the following steps: providing one or more materials, the one or more materials having at least one surface and a material layer adjacent to said surface, wherein said surface comprises highly spin-polarized surface electrons, wherein the direction and spin of the surface electrons are locked together; providing at least one incident light capable of stimulating photoemission of said surface electrons; wherein the photon polarization of said incident light is tunable; and inducing photoemission of the surface electron states.
摘要翻译：一个或多个实施方案一般涉及光电子自旋的领域，更具体地涉及用于产生可控自旋极化电子源的方法和系统。本发明的一个优选实施方案通常包括：用于产生可控自旋极化电子源的方法，包括以下步骤：提供一种或多种材料，所述一种或多种材料具有至少一个表面和与所述表面相邻的材料层，其中所述表面包括高自旋极化表面电子，其中表面电子的方向和自旋锁定在一起; 提供能够刺激所述表面电子的光电子发射的至少一个入射光; 其中所述入射光的光子偏振是可调的; 并诱导表面电子态的光电子发射。

8. 发明申请

US20150235799A1 VERSATILE SPIN-POLARIZED ELECTRON SOURCE 有权
标题翻译：多极旋转极化电子源
公开(公告)号：US20150235799A1
公开(公告)日：2015-08-20
申请号：US14185651
申请日：2014-02-20
申请人： Chris Jozwiak , Cheol Hwan Park , Kenneth Gotlieb , Steven Gwon Sheng Louie , Zahid Hussain , Alessandra Lanzara
发明人： Chris Jozwiak , Cheol Hwan Park , Kenneth Gotlieb , Steven Gwon Sheng Louie , Zahid Hussain , Alessandra Lanzara
IPC分类号： H01J1/34 , H01J43/18 , H01J40/16 , H01J1/36
CPC分类号： H01L29/66007 , G21K1/16 , H01J1/34 , H01L29/66984
摘要： One or more embodiments relate generally to the field of photoelectron spin and, more specifically, to a method and system for creating a controllable spin-polarized electron source. One preferred embodiment of the invention generally comprises: method for creating a controllable spin-polarized electron source comprising the following steps: providing one or more materials, the one or more materials having at least one surface and a material layer adjacent to said surface, wherein said surface comprises highly spin-polarized surface electrons, wherein the direction and spin of the surface electrons are locked together; providing at least one incident light capable of stimulating photoemission of said surface electrons; wherein the photon polarization of said incident light is tunable; and inducing photoemission of the surface electron states.
摘要翻译：一个或多个实施方案一般涉及光电子自旋的领域，更具体地涉及用于产生可控自旋极化电子源的方法和系统。本发明的一个优选实施方案通常包括：用于产生可控自旋极化电子源的方法，包括以下步骤：提供一种或多种材料，所述一种或多种材料具有至少一个表面和与所述表面相邻的材料层，其中所述表面包括高度自旋极化的表面电子，其中表面电子的方向和自旋锁定在一起; 提供能够刺激所述表面电子的光电子发射的至少一个入射光; 其中所述入射光的光子偏振是可调的; 并诱导表面电子态的光电子发射。

9. 发明授权

US08470668B2 Method for forming pillar type capacitor of semiconductor device 有权
标题翻译：半导体器件柱状电容器形成方法
公开(公告)号：US08470668B2
公开(公告)日：2013-06-25
申请号：US12979926
申请日：2010-12-28
申请人： Ho Jin Cho , Cheol Hwan Park , Dong Kyun Lee
发明人： Ho Jin Cho , Cheol Hwan Park , Dong Kyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/90
摘要： An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.
摘要翻译：本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。然后在电介质膜的上部上形成顶部电极。

10. 发明授权

US07985645B2 Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same 有权
标题翻译：具有高方位圆柱形电容器的半导体器件及其制造方法
公开(公告)号：US07985645B2
公开(公告)日：2011-07-26
申请号：US12649610
申请日：2009-12-30
申请人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
发明人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L27/10894
摘要： A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
摘要翻译：提出了具有高方位圆柱形电容器的半导体器件及其制造方法。高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。存储节点氧化物位于半导体衬底上的周边区域中。导电层涂覆保护环孔。在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。覆盖氧化物部分地填充导电层的一部分。间隙填充膜填充在导电层的其余部分。

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