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1. 发明授权

US06393446B1 32-bit and 64-bit dual mode rotator 失效
标题翻译： 32位和64位双模旋转器
公开(公告)号：US06393446B1
公开(公告)日：2002-05-21
申请号：US09343450
申请日：1999-06-30
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Joel Abraham Silberman
IPC分类号： G06F700
CPC分类号： G06F7/762 , G06F5/015
摘要： A dual mode rotator capable of performing 32-bit and 64-bit rotation. According to a preferred embodiment, the dual mode rotator includes a first, second, and third rotator units wherein each rotator has a plurality of inputs and outputs. The inputs of the second rotator are operatively connected to the corresponding outputs of the first rotator unit. The inputs of the third rotator unit are operatively connected to the corresponding outputs of the second rotator. Responsive to selection of 32-bit rotation mode, the upper half of the inputs to the first rotator are zero and the lower half of the outputs of the third rotator are replicated in the upper half of the outputs of the third rotator.
摘要翻译：能够执行32位和64位旋转的双模旋转器。根据优选实施例，双模旋转器包括第一，第二和第三旋转单元，其中每个旋转器具有多个输入和输出。第二旋转器的输入可操作地连接到第一旋转单元的相应输出端。第三旋转单元的输入可操作地连接到第二旋转器的相应输出。响应于选择32位旋转模式，第一旋转器的输入的上半部分为零，并且第三旋转器的输出的下半部分被复制在第三旋转器的输出的上半部分中。

2. 发明授权

US5964827A High-speed binary adder 失效
标题翻译：高速二进制加法器
公开(公告)号：US5964827A
公开(公告)日：1999-10-12
申请号：US971653
申请日：1997-11-17
申请人： Hung Cai Ngo , Sang Hoo Dhong , Joel Abraham Silberman
发明人： Hung Cai Ngo , Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F7/50 , G06F7/508 , G06F7/52
CPC分类号： G06F7/508
摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
摘要翻译：公开了一种高速进位 - 前瞻二进制加法器。二进制加法器包括多行进位查找电路，半和模块和和/进位模块。第一进位 - 前瞻电路行包括多个四位组生成电路和多个四位组传播电路。四位组生成电路中的每一个产生相应位位置的生成信号。四位组传播电路中的每一个产生用于相应位位置的传播信号。半和模块用于产生半和信号。通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

3. 发明授权

US06232872B1 Comparator 失效
标题翻译：比较器
公开(公告)号：US06232872B1
公开(公告)日：2001-05-15
申请号：US09418377
申请日：1999-10-14
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park
IPC分类号： G06F702
CPC分类号： G06F7/026 , G06F12/0895
摘要： A 64-bit comparator includes a first stage for receiving a 64-bit number A and a 64-bit number B, and generating first output values. A second stage then receives the first output values from the first stage and outputs second output values, and a third stage receives the second output values from the second stage and outputs greater than, less than, and equivalent values. Thus, the comparator is faster in that it is implemented in three logic stages by making efficient use of compound dynamic gates.
摘要翻译： 64位比较器包括用于接收64位数字A和64位数字B的第一级，并且产生第一输出值。然后，第二级接收来自第一级的第一输出值并输出第二输出值，第三级从第二级接收第二输出值，并输出大于，小于和等效的值。因此，比较器更快，因为它通过有效地使用复合动态门在三个逻辑阶段中被实现。

4. 发明授权

US06360238B1 Leading zero/one anticipator having an integrated sign selector 失效
标题翻译：领先的零/一个预测器具有集成的符号选择器
公开(公告)号：US06360238B1
公开(公告)日：2002-03-19
申请号：US09270469
申请日：1999-03-15
申请人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F501
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.
摘要翻译：公开了具有集成符号选择器的零/一预测器。通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。前导零字符串为正和，前导字符串为负数。然后从前导零字符串和前导字符串确定归一化偏移量。然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。然后，利用该符号来选择正和或负的正和归一化移位量。

5. 发明授权

US06285218B1 Method and apparatus for implementing logic using mask-programmable dynamic logic gates 有权
标题翻译：使用掩码可编程动态逻辑门实现逻辑的方法和装置
公开(公告)号：US06285218B1
公开(公告)日：2001-09-04
申请号：US09567381
申请日：2000-05-10
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
IPC分类号： H03K19094
CPC分类号： H03K19/1736
摘要： A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.
摘要翻译：用于用可编程动态逻辑门实现动态逻辑的方法和装置作为用于高速微处理器设计中的可编程逻辑阵列（PLA）的补充。可选单元的矩阵提供强大的逻辑功能，例如具有最小输入和晶体管的AND-OR门能力。通过使用可编程逻辑阵列和可编程动态门，逻辑块的效率可以大大提高，几乎没有增加电路面积。

6. 发明授权

US06282557B1 Low latency fused multiply-adder 失效
标题翻译：低延迟融合乘法加法器
公开(公告)号：US06282557B1
公开(公告)日：2001-08-28
申请号：US09207483
申请日：1998-12-08
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F748
CPC分类号： G06F7/5443 , G06F7/5318
摘要： A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.
摘要翻译：公开了一种用于将第一二进制数和第二二进制数的乘积加到第三个二进制数的低延迟融合乘法加法器。低延迟融合乘法器包括部分乘积生成模块，部分乘积减少模块和进位传播加法器。部分乘积生成模块从第一二进制数和第二二进制数生成一组部分乘积。与部分产品生成模块相结合，部分产品减少模块将部分产品集合与第三个二进制数组合，以产生冗余Sum和冗余进位。最后，进位传播加法器将冗余Sum和冗余Carry相加，得到Sum Total。

7. 发明授权

US06175852B1 High-speed binary adder 失效
标题翻译：高速二进制加法器
公开(公告)号：US06175852B1
公开(公告)日：2001-01-16
申请号：US09114117
申请日：1998-07-13
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F750
CPC分类号： G06F7/508
摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
摘要翻译：公开了一种高速进位 - 前瞻二进制加法器。二进制加法器包括多行进位查找电路，半和模块和和/进位模块。第一进位 - 前瞻电路行包括多个8位组生成电路和多个8位组传播电路。八位组生成电路中的每一个产生相应位位置的生成信号。八位组传播电路中的每一个产生相应位位置的传播信号。半和模块用于产生半和信号。通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

8. 发明授权

US06345286B1 6-to-3 carry-save adder 失效
标题翻译：一个6对3进位保存加法器
公开(公告)号：US06345286B1
公开(公告)日：2002-02-05
申请号：US09182593
申请日：1998-10-30
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F750
CPC分类号： G06F7/607 , G06F2207/3872
摘要： A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. The first data output is a SUM output, the second data output is a CARRY—2 output, and the third data output is a CARRY—4 output.
摘要翻译：公开了一种6比3的进位保存二进制加法器。 6对3进位存储加法器包括用于接收六个数据输入的装置和用于同时添加六个数据输入以产生第一数据输出，第二数据输出和第三数据输出的装置。第一个数据输出是一个SUM输出，第二个数据输出是一个CARRY-2输出，第三个数据输出是一个CARRY-4输出。

9. 发明授权

US06178437B1 Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor 失效
标题翻译：用于预测浮点处理器中的前导数字和归一化移位量的方法和装置
公开(公告)号：US06178437B1
公开(公告)日：2001-01-23
申请号：US09139940
申请日：1998-08-25
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F742
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.
摘要翻译：公开了一种用于预测浮点处理器中的前导零/一个的方法。通过检查两个输入操作数的两个相邻位的进位传播，生成和杀死浮点处理器内的加法器来产生前导零字符串和前导字符串。前导零字符串为正和，前导字符串为负数。在确定正和和负的和的输出的符号之前，从前导零字符串和前导字符串直接并发地计算归一化偏移量。

10. 发明授权

US07995418B2 Method and computer program for controlling a storage device having per-element selectable power supply voltages 有权
标题翻译：用于控制具有每元件可选电源电压的存储装置的方法和计算机程序
公开(公告)号：US07995418B2
公开(公告)日：2011-08-09
申请号：US12399551
申请日：2009-03-06
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

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