专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06775640B1 Performance adder for tracking occurrence of events within a circuit 失效
标题翻译：用于跟踪电路内事件发生的性能加法器
公开(公告)号：US06775640B1
公开(公告)日：2004-08-10
申请号：US09560189
申请日：2000-04-28
申请人： Jeffrey C. Swanson , John A. Wickeraad
发明人： Jeffrey C. Swanson , John A. Wickeraad
IPC分类号： G06F742
CPC分类号： G06F11/348 , G06F2201/88
摘要： A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can also trigger the performance adder through atomic, edge, toggle, or on/off signals related to the performance events or through a logical function of a combination of performance events. The performance adders can be used to compute average latency of a component in the circuit.
摘要翻译：一种性能加法器，用于在集成电路芯片内提供运行中的性能值总计。性能加法器由通过多路复用器逻辑确定的各种性能事件触发，用于检测特定性能事件的发生。复用器逻辑还可以通过与性能事件相关的原子，边沿，触发或开/关信号或通过性能事件的组合的逻辑功能来触发性能加法器。性能加法器可用于计算电路中组件的平均延迟。

2. 发明授权

US06754688B2 Method and apparatus to calculate the difference of two numbers 有权
标题翻译：计算两个数字差异的方法和装置
公开(公告)号：US06754688B2
公开(公告)日：2004-06-22
申请号：US09783235
申请日：2001-02-14
申请人： Giao Pham , Mathew J. Parker
发明人： Giao Pham , Mathew J. Parker
IPC分类号： G06F742
CPC分类号： G06F7/485 , G06F5/012 , G06F7/026
摘要： An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the first detection bits indicate a difference of zero. A second module generates second detection bits from the first and second operands, where the second detection bits indicate a difference of one. A combiner combines the first and second detection bits to determine whether the difference of two numbers is less than two. The apparatus and method is used in determining to bypass normalization in floating point calculation.
摘要翻译：公开了一种用于确定两个操作数是否小于2的装置和方法。第一模块从第一操作数和第二操作数产生第一检测位，其中第一检测位指示零差值。第二模块从第一和第二操作数产生第二检测位，其中第二检测位指示一差异。组合器组合第一和第二检测位以确定两个数字的差异是否小于2。该装置和方法用于确定在浮点计算中绕过规范化。

3. 发明授权

US06246279B1 Output amplitude control circuit 有权
标题翻译：输出幅度控制电路
公开(公告)号：US06246279B1
公开(公告)日：2001-06-12
申请号：US09428612
申请日：1999-10-27
申请人： Takanori Komuro
发明人： Takanori Komuro
IPC分类号： G06F742
CPC分类号： H03M1/70
摘要： The invention presents a circuit by which control of the output amplitude of digital analog converters can be carried out at high speed and with high precision. A first digital signal that is the same as the input signal and a second digital signal of a value slightly smaller than an input signal provided from a high-speed processor are selectively applied to plural D-A converters and the output therefrom is added. By changing the ratio with which the first digital signal and the second digital signal are selected, it is possible to control the analog output amplitude.
摘要翻译：本发明提出了一种可以高速，高精度地进行数字模拟转换器输出振幅的控制的电路。与输入信号相同的第一数字信号和稍微小于从高速处理器提供的输入信号的值的第二数字信号被选择性地施加到多个D-A转换器，并且添加其输出。通过改变选择第一数字信号和第二数字信号的比率，可以控制模拟输出幅度。

4. 发明授权

US06578060B2 Floating-point calculation apparatus 有权
标题翻译：浮点计算装置
公开(公告)号：US06578060B2
公开(公告)日：2003-06-10
申请号：US09275079
申请日：1999-03-24
申请人： Addison Chen , Hiroaki Suzuki
发明人： Addison Chen , Hiroaki Suzuki
IPC分类号： G06F742
CPC分类号： G06F7/485
摘要： A value of difference between exponent values and an inverted value thereof obtained by an inverting circuit are calculated using one subtractor and one of the value of the difference and the inverted value of the difference is selected in accordance with a signal indicating which of the exponent values is greater. Only one subtractor is used, so that the scale of the circuit is reduced and the reduction in chip real estate and power consumption can be achieved. Thus, a circuit for calculating an absolute value of difference between exponent values for right-shifting a floating-point number is provided, with reduced chip real estate and power consumption.
摘要翻译：通过使用一个减法器来计算由反相电路获得的指数值和反相值之间的差异值，并且根据指示哪个指数值的信号来选择差值的值和反转值之一更伟大。仅使用一个减法器，从而减小电路规模，并且可以实现芯片的不动产和功耗的降低。因此，提供了用于计算用于右移浮点数的指数值之间的差异的绝对值的电路，具有减少的芯片不动产和功耗。

5. 发明授权

US06529928B1 Floating-point adder performing floating-point and integer operations 有权
标题翻译：浮点加法器执行浮点和整数运算
公开(公告)号：US06529928B1
公开(公告)日：2003-03-04
申请号：US09274595
申请日：1999-03-23
申请人： David R. Resnick , William T. Moore
发明人： David R. Resnick , William T. Moore
IPC分类号： G06F742
CPC分类号： G06F7/505 , G06F7/485 , G06F2207/3824
摘要： An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation. The floating-point adder permits all integer add, subtract and compare operations be performed by the floating-point adder without adding substantial additional hardware to the arithmetic logic unit.
摘要翻译：公开了一种利用单个功能单元执行浮点运算和整数运算的装置和方法。浮点加法器执行用于比较指数的逻辑，用于选择和移位合成的逻辑，以及用于添加系数的逻辑。在操作中，浮点加法器单元使用与用于浮点运算的基本上相同的硬件来执行整数加，减和比较运算。用于比较指数的逻辑的输出表示整数运算结果的最高有效位。用于添加系数的逻辑的输出表示整数运算结果的最低有效位。如果存在用于添加系数的逻辑的进位，则将进位的值加到表示整数运算的最高有效位的部分结果中。浮点加法器允许通过浮点加法器执行所有整数加法，减法和比较运算，而不向算术逻辑单元增加实质的附加硬件。

6. 发明授权

US06397239B2 Floating point addition pipeline including extreme value, comparison and accumulate functions 有权
标题翻译：浮点附加流水线包括极值，比较和累加功能
公开(公告)号：US06397239B2
公开(公告)日：2002-05-28
申请号：US09778352
申请日：2001-02-06
申请人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna Cherukuri
发明人： Stuart F. Oberman , Norbert Juffa , Fred Weber , Krishnan Ramani , Ravi Krishna Cherukuri
IPC分类号： G06F742
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30036 , H03M7/24
摘要： A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.
摘要翻译：多媒体执行单元被配置为执行矢量的浮点和整数指令。执行单元可以包括具有远近数据路径的加法/减法流水线。远程路径被配置为处理具有大于1的绝对指数差的操作数的有效加法运算和有效减法运算。关闭路径被配置为处理具有小于或等于1的绝对指数差的操作数的有效减法操作。关闭路径被配置为生成两个输出值，其中一个输出值是第一输入操作数加上第二输入操作数的反转版本，而第二输出值等于第一输出值加1。在闭合路径中选择第一或第二输出值对加法器的输出实现了舍入到最近的运算。

7. 发明授权

US06721773B2 Single precision array processor 有权
标题翻译：单精度阵列处理器
公开(公告)号：US06721773B2
公开(公告)日：2004-04-13
申请号：US10167004
申请日：2002-06-10
申请人： Earle W. Jennings, III
发明人： Earle W. Jennings, III
IPC分类号： G06F742
CPC分类号： G06F15/7857 , G06F7/483 , G06F7/5443
摘要： An arithmetic circuit for calculating floating point operations. The circuit comprises first and second blocks of consecutive logic cells. Each logic block has a first cell and a last cell, with the first cell through the next to last cell having an output that is coupled to the next adjacent cell. The coupling of the last cells of the first and second logic blocks depends on the value of a control signal. A comparator may be used to generate the control signal.
摘要翻译：一种用于计算浮点运算的运算电路。该电路包括连续逻辑单元的第一和第二块。每个逻辑块具有第一小区和最后一个小区，其中第一个小区通过下一个到最后一个小区具有耦合到下一个相邻小区的输出。第一和第二逻辑块的最后一个单元的耦合取决于控制信号的值。可以使用比较器来产生控制信号。

8. 发明授权

US06571267B1 Floating point addition/subtraction execution unit 失效
标题翻译：浮点加法/减法执行单元
公开(公告)号：US06571267B1
公开(公告)日：2003-05-27
申请号：US09521891
申请日：2000-03-09
申请人： Shinichi Yoshioka
发明人： Shinichi Yoshioka
IPC分类号： G06F742
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： In a floating point execution unit capable of executing arithmetic operation at high speed, a canceling prediction circuit (60) inputs directly operands before processing of selectors (2 and 3) and predicts a canceling generated in a subtraction result of the operands executed by a subtraction unit (5). The canceling prediction circuit (60) performs the canceling prediction without waiting the completion of carry adjustment of the operands executed by selecting and then executing the selectors (2 and 3). In addition, the prediction error detection circuit (100). Accordingly, when the subtraction result of the subtraction circuit (5) is output through a selector (12), or before the subtraction result is output, the canceling prediction can be executed. Thereby, the left shifter (8) can execute normalization operation for the subtraction result. without waiting, and the error compensation shifter (9) can also execute the compensation operation of the canceling prediction without waiting by using a compensation signal output from the prediction error detection circuit (100).
摘要翻译：在能够高速执行算术运算的浮点执行单元中，消除预测电路（60）在选择器（2和3）处理之前直接输入操作数，并且预测在减法执行的操作数的减法结果中产生的抵消单位（5）。取消预测电路（60）在不等待通过选择并执行选择器（2和3）执行的操作数的进位调整的完成的情况下执行取消预测。另外，预测误差检测电路（100）。因此，当减法电路（5）的减法结果通过选择器（12）输出时，或在减法结果输出之前，可以执行取消预测。由此，左移位器（8）可以对减法结果执行归一化操作。无需等待，误差补偿移位器（9）也可以在不等待使用从预测误差检测电路（100）输出的补偿信号的情况下执行取消预测的补偿操作。

9. 发明授权

US06275839B1 Method and system for immediate exponent normalization in a fast floating point adder 有权
标题翻译：快速浮点加法器中立即指数归一化的方法和系统
公开(公告)号：US06275839B1
公开(公告)日：2001-08-14
申请号：US09173316
申请日：1998-10-15
申请人： Günter Gerwig , Klaus Jörg Getzlaff , Michael Kröner
发明人： Günter Gerwig , Klaus Jörg Getzlaff , Michael Kröner
IPC分类号： G06F742
CPC分类号： G06F7/485 , G06F7/49936
摘要： A method and system for use in a data processing system is proposed, wherein the Input Exponent is used already in the subblocks of the mantissa addition. Early in the flow of a cycle, there are parts of the Potential exponent result generated and put together using zero detect signals and carry select signals of the Carry Select Adder of the mantissa addition. For the addition of two floating point numbers this reduces the number of required logic gates in the timing critical path. This allows a faster cycle time and/or less latency and/or more complex functions. The method and system according to the invention can be applied to adders of different mantissa widths or different exponent widths as well as power of radix 2.
摘要翻译：提出了一种在数据处理系统中使用的方法和系统，其中输入指数已经在尾数加法的子块中使用。在一个周期的流程中，有一部分电位指数结果生成并使用零检测信号放在一起，并携带尾数加法器的加法选择加法器的选择信号。为了增加两个浮点数，这减少了时序关键路径中所需逻辑门的数量。这允许更快的周期时间和/或更少的等待时间和/或更复杂的功能。根据本发明的方法和系统可以应用于不同尾数宽度或不同指数宽度的加法器以及基数2的幂。

10. 发明授权

US06178437B1 Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor 失效
标题翻译：用于预测浮点处理器中的前导数字和归一化移位量的方法和装置
公开(公告)号：US06178437B1
公开(公告)日：2001-01-23
申请号：US09139940
申请日：1998-08-25
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F742
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.
摘要翻译：公开了一种用于预测浮点处理器中的前导零/一个的方法。通过检查两个输入操作数的两个相邻位的进位传播，生成和杀死浮点处理器内的加法器来产生前导零字符串和前导字符串。前导零字符串为正和，前导字符串为负数。在确定正和和负的和的输出的符号之前，从前导零字符串和前导字符串直接并发地计算归一化偏移量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式