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1. 发明申请

US20050003630A1 Trench isolation without grooving 有权
标题翻译：沟槽隔离无槽
公开(公告)号：US20050003630A1
公开(公告)日：2005-01-06
申请号：US10901948
申请日：2004-07-29
申请人： Hua Ji , Dong Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
摘要翻译：提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。特别地，一种方法包括两步氧化法，其中氧化物衬垫在沟槽的内表面上划线，并且沟槽填充有本体氧化物层，优选使用高密度等离子体化学气相沉积（HDP-CVD）工艺。氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。因此，当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时，形成基本平坦且没有凹槽的公共电介质顶表面。

2. 发明授权

US06924542B2 Trench isolation without grooving 有权
公开(公告)号：US06924542B2
公开(公告)日：2005-08-02
申请号：US10901948
申请日：2004-07-29
申请人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L21/762 , H01L29/00 , H01L21/8238
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

3. 发明授权

US06787409B2 Method of forming trench isolation without grooving 有权
标题翻译：无沟槽形成沟槽隔离的方法
公开(公告)号：US06787409B2
公开(公告)日：2004-09-07
申请号：US10305464
申请日：2002-11-26
申请人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L218238
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
摘要翻译：提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。特别地，一种方法包括两步氧化法，其中氧化物衬垫在沟槽的内表面上划线，并且沟槽填充有本体氧化物层，优选使用高密度等离子体化学气相沉积（HDP-CVD）工艺。氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。因此，当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时，形成基本平坦且没有凹槽的公共电介质顶表面。

4. 发明授权

US07709386B2 Atomic layer deposition method and semiconductor device formed by the same 有权
标题翻译：原子层沉积法和由其形成的半导体器件
公开(公告)号：US07709386B2
公开(公告)日：2010-05-04
申请号：US12141045
申请日：2008-06-17
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
IPC分类号： H01L21/44
CPC分类号： H01L21/0228 , C23C16/45529 , H01L21/0214 , H01L21/0217 , H01L21/02211 , H01L21/28282 , H01L21/3141 , H01L21/31645 , H01L21/318 , H01L21/3185 , H01L27/11563
摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.
摘要翻译：提供了一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的介电层。

5. 发明申请

US20120043886A1 Integrated Heat Conductive Light Emitting Diode (LED) White Light Source Module 审中-公开
标题翻译：集成导热发光二极管（LED）白光源模块
公开(公告)号：US20120043886A1
公开(公告)日：2012-02-23
申请号：US13098797
申请日：2011-05-02
申请人： Hua Ji , Robert Nail Lee
发明人： Hua Ji , Robert Nail Lee
IPC分类号： H01J7/44 , H01J7/24
CPC分类号： H01L25/0753 , H01L33/60 , H01L33/641 , H01L2224/48091 , H05K1/021 , H05K2201/10106 , H01L2924/00014
摘要： This invention discloses a new and advanced light emitting diodes (LEDs) light source module, and more specifically surface mounting LED dice and/or driver circuits on a slim linear Silicon wafer to provide superior heat dissipation capability through eutectic bonding onto a small Silicon base and the overall performance/cost ratio of the LED white light source module by an advanced integrated.
摘要翻译：本发明公开了一种新型和先进的发光二极管（LED）光源模块，更具体地说，在薄型线性硅晶片上表面安装LED芯片和/或驱动电路，以通过共晶接合到小硅基底上提供优异的散热能力， LED白光源模块的整体性能/成本比先进集成。

6. 发明申请

US20060051951A1 Method of clearing electrical contact pads in thin film sealed OLED devices 有权
标题翻译：在薄膜密封OLED器件中清除电接触焊盘的方法
公开(公告)号：US20060051951A1
公开(公告)日：2006-03-09
申请号：US11169154
申请日：2005-06-27
申请人： Amalkumar Ghosh , Yachin Liu , Hua Ji
发明人： Amalkumar Ghosh , Yachin Liu , Hua Ji
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L21/02098 , H01L24/05 , H01L24/85 , H01L27/3297 , H01L2224/8501 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2224/48 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.
摘要翻译：清洁与OLED器件相关联的引线接合焊盘的过程，包括以下步骤：在引线接合焊盘上沉积一层或多层可消融材料，以及用激光烧蚀一层或多层，从而暴露清洁的焊线焊盘。

7. 发明授权

US08273639B2 Atomic layer deposition method and semiconductor device formed by the same 有权
标题翻译：原子层沉积法和由其形成的半导体器件
公开(公告)号：US08273639B2
公开(公告)日：2012-09-25
申请号：US12132459
申请日：2008-06-03
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
IPC分类号： H01L21/20
CPC分类号： C23C16/04 , C23C16/45527 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28282 , H01L21/3141 , H01L21/31616 , H01L21/3185
摘要： Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.
摘要翻译：公开了原子层沉积方法和包括原子层的半导体器件，包括以下步骤：将半导体衬底放置在原子层沉积室中; 将第一前体气体供给到腔室内的半导体衬底，以在半导体衬底上形成第一离散单层; 向腔室内的半导体衬底供给惰性清洗气体以去除在半导体衬底上未形成第一离散单层的第一前体气体; 将第二前体气体供给到所述室中以与形成所述第一离散单层的所述第一前体气体反应，形成离散的原子尺寸岛; 以及将惰性吹扫气体供给到室内的半导体衬底以除去未与第一前体气体反应的第二前体气体和由第一和第二前体气体之间的反应产生的副产物。

8. 发明申请

US20120168853A1 SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：半导体非易失性存储器件
公开(公告)号：US20120168853A1
公开(公告)日：2012-07-05
申请号：US13419943
申请日：2012-03-14
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno , Seanfuxiong Zhang
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno , Seanfuxiong Zhang
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , C23C16/45529 , H01L29/1608 , H01L29/40117 , H01L29/42348
摘要： A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method.
摘要翻译：一种半导体非易失性存储器（NVM）器件，包括：半导体衬底; 设置在半导体衬底上的中层电荷俘获层 - 介质层的三层堆叠结构; 设置在三层堆叠结构上方的栅极; 在三层堆叠结构的任一侧设置在半导体衬底中的源极和漏极; 其中电荷捕获层是包含通过原子层沉积（ALD）方法形成的一个或多个离散化合物簇的电介质层。

9. 发明授权

US06740571B2 Method of etching a dielectric material in the presence of polysilicon 有权
标题翻译：在多晶硅存在下蚀刻电介质材料的方法
公开(公告)号：US06740571B2
公开(公告)日：2004-05-25
申请号：US10202992
申请日：2002-07-25
申请人： Hua Ji
发明人： Hua Ji
IPC分类号： H01L213205
CPC分类号： H01L21/76229 , H01L21/28123 , H01L21/31111 , H01L21/76237 , H01L21/823878
摘要： A method is provided for advantageously etching dielectric material between highly integrated polysilicon devices with high dielectric-to-polysilicon selectivity to expose polysilicon with minimal polysilicon loss and without photoresist lift. A wet etch solution comprising surfactant and between about 0% and about 10% NH4F is used to wet etch the dielectric material and reduce polysilicon loss thickness, polysilicon resistance ratios, and polysilicon etch rates, while increasing dielectric-to-polysilicon selectivity. Advantageously, the present invention may penetrate into increasingly small geometries of highly integrated devices and may also be used for general wet etches of dielectric material in conjunction with photoresist.
摘要翻译：提供了一种有利地在高度集成的多晶硅器件之间蚀刻介电材料的方法，其具有高的电介质至多晶硅的选择性，以最小的多晶硅损耗和无光致抗蚀剂提升来露出使用包含表面活性剂和约0％至约10％NH 4 F的湿蚀刻溶液来湿法蚀刻介电材料并减少多晶硅损耗厚度，多晶硅电阻比和多晶硅蚀刻速率，同时增加电介质至多晶硅的选择性。有利地，本发明可以渗透到越来越小的高度集成的器件的几何形状中，并且还可以用于与光致抗蚀剂结合的介电材料的一般湿蚀刻。

10. 发明授权

US08516493B2 System and method for massively multi-core computing systems 有权
标题翻译：用于大型多核计算系统的系统和方法
公开(公告)号：US08516493B2
公开(公告)日：2013-08-20
申请号：US13019303
申请日：2011-02-01
申请人： Nitin Hande , Hua Ji , Kais Belgaied
发明人： Nitin Hande , Hua Ji , Kais Belgaied
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/5022 , G06F2209/5011 , G06F2209/5022 , Y02D10/22
摘要： A system and method for massively multi-core computing are provided. A method for computer management includes determining if there is a need to allocate at least one first resource to a first plane. If there is a need to allocate at least one first resource, the at least one first resource is selected from a resource pool based on a set of rules and allocated to the first plane. If there is not a need to allocate at least one first resource, it is determined if there is a need to de-allocate at least one second resource from a second plane. If there is a need to de-allocate at least one second resource, the at least one second resource is de-allocated. The first plane includes a control plane and/or a data plane and the second plane includes the control plane and/or the data plane. The resources are unchanged if there is not a need to allocate at least one first resource and if there is not a need to de-allocate at least one second resource.
摘要翻译：提供了一种用于大规模多核心计算的系统和方法。一种用于计算机管理的方法包括确定是否需要将至少一个第一资源分配给第一平面。如果需要分配至少一个第一资源，则基于一组规则从资源池中选择至少一个第一资源并将其分配给第一平面。如果不需要分配至少一个第一资源，则确定是否需要从第二平面去分配至少一个第二资源。如果需要去分配至少一个第二资源，则至少一个第二资源被去分配。第一平面包括控制平面和/或数据平面，第二平面包括控制平面和/或数据平面。如果不需要分配至少一个第一资源，并且如果不需要去分配至少一个第二资源，则资源是不变的。

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