会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Method of forming trench isolation without grooving
    • 无沟槽形成沟槽隔离的方法
    • US06787409B2
    • 2004-09-07
    • US10305464
    • 2002-11-26
    • Hua JiDong Jun KimJin-Ho KimChuck Jang
    • Hua JiDong Jun KimJin-Ho KimChuck Jang
    • H01L218238
    • H01L21/76229
    • A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
    • 提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。 特别地,一种方法包括两步氧化法,其中氧化物衬垫在沟槽的内表面上划线,并且沟槽填充有本体氧化物层,优选使用高密度等离子体化学气相沉积(HDP-CVD)工艺 。 氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。 因此,当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时,形成基本平坦且没有凹槽的公共电介质顶表面。
    • 6. 发明授权
    • Substrate isolation in integrated circuits
    • 集成电路中的基板隔离
    • US07358149B2
    • 2008-04-15
    • US11193150
    • 2005-07-29
    • Daniel WangChunchieh HuangDong Jun Kim
    • Daniel WangChunchieh HuangDong Jun Kim
    • H01L21/425
    • H01L27/11526H01L21/76237H01L21/823481H01L27/105H01L27/11539H01L27/11546
    • Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.
    • 衬底隔离沟槽(224)形成在半导体衬底(120)中。 通过离子注入将掺杂剂(例如硼)注入到沟槽侧壁中,以抑制沿着侧壁的电流泄漏。 在离子注入期间,晶体管栅极电介质(520)面向离子流,但在随后的热步骤中对栅极电介质的损坏退火。 在一些实施例中,掺杂剂注入是成角度的植入物。 植入物从晶片的相对侧进行,并且因此从每个有效区域的相对侧进行。 每个有源区域包括从一侧注入的区域和从相对侧注入的区域。 两个区域重叠以便于阈值电压调整。
    • 9. 发明授权
    • Method of manufacturing capacitor of semiconductor device
    • 制造半导体器件电容器的方法
    • US06339009B1
    • 2002-01-15
    • US09708456
    • 2000-11-09
    • Kee Jeung LeeDong Jun Kim
    • Kee Jeung LeeDong Jun Kim
    • H01L2120
    • H01L28/55H01L21/31604H01L21/31691H01L28/90
    • The present invention discloses a method of manufacturing a capacitor of high capacitance using a (Ta2O5)1−x(TiO2)x thin film as dielectric layer. The method according to the present invention, comprising providing a semiconductor substrate over which selected lower patterns are formed and an intermediate insulating layer is covered; forming a lower electrode on the intermediate insulating layer; depositing a (Ta2O5)1−x—(TiO2)x thin film in an amorphous state on the lower electrode; annealing the amorphous (Ta2O5)1−x—(TiO2)x thin film at a low temperature; annealing the low temperature amorphous (Ta2O5)1−x—(TiO2)x thin film at a high temperature to form a crystalline (Ta2O5)1−x—(TiO2)x thin film as a dielectric layer; and forming an upper electrode on the (Ta2O5)1−x—(TiO2)x thin film.
    • 本发明公开了使用(Ta 2 O 5)1-x(TiO 2)x薄膜作为电介质层制造高电容电容器的方法。 根据本发明的方法,包括提供半导体衬底,在其上形成选定的下部图案并覆盖中间绝缘层; 在中间绝缘层上形成下电极; 在下电极上沉积非晶态的(Ta 2 O 5)1-x-(TiO 2)x薄膜; 在低温下退火无定形(Ta2O5)1-x-(TiO2)x薄膜; 在高温下对低温无定形(Ta 2 O 5)1-x-(TiO 2)x薄膜进行退火以形成作为介电层的结晶(Ta 2 O 5)1-x-(TiO 2)x薄膜; 并在(Ta 2 O 5)1-x-(TiO 2)x薄膜上形成上电极。