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1. 发明授权

US5818082A E.sup.2 PROM device having erase gate in oxide isolation region in shallow trench and method of manufacture thereof 失效
标题翻译： E2PROM器件在浅沟槽中的氧化物隔离区域中具有擦除栅极及其制造方法
公开(公告)号：US5818082A
公开(公告)日：1998-10-06
申请号：US610688
申请日：1996-03-04
申请人： Hsingya Arthur Wang , Jein-Chen Young , Darlene Hamilton
发明人： Hsingya Arthur Wang , Jein-Chen Young , Darlene Hamilton
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/78
CPC分类号： H01L27/11517 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： An E.sup.2 PROM device includes a semiconductor body having source and drain regions and a channel region, with a gate oxide over the channel region and a floating gate over the gate oxide. An oxide isolation region contains a doped polysilicon erase gate, so that erasing of the device takes place by electron flow from the floating gate to the erase gate through a thin oxide portion of the oxide isolation region, at a position spaced from the gate oxide. The inclusion of the erase gate in the oxide isolation region results in smaller overall device size than previously achieved.
摘要翻译： E2PROM器件包括具有源极和漏极区域以及沟道区域的半导体本体，沟道区域上具有栅极氧化物，栅极氧化物上方具有浮动栅极。氧化物隔离区域包含掺杂的多晶硅擦除栅极，使得器件的擦除是通过电子从与栅极氧化物隔开的位置通过氧化物隔离区域的氧化物部分从浮动栅极流向擦除栅极而发生的。在氧化物隔离区域中包括擦除栅极导致比先前实现的更小的整体器件尺寸。

2. 发明授权

US08941094B2 Methods for adjusting the conductivity range of a nanotube fabric layer 有权
标题翻译：调整纳米管织物层电导率范围的方法
公开(公告)号：US08941094B2
公开(公告)日：2015-01-27
申请号：US12874501
申请日：2010-09-02
申请人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
发明人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
IPC分类号： H01L45/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/00 , H01L51/44
CPC分类号： H01L45/149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/0015 , H01L51/0048 , H01L51/444 , Y02E10/549
摘要： Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
摘要翻译：公开了调整和/或限制纳米管织物层的电导率范围的方法。在一些方面，通过湿法化学技术使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过等离子体处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过CVD处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，纳米管织物层的导电性通过惰性离子注入物官能化织物层内的纳米管元件来调节。

3. 发明授权

US08264898B2 Controlling AC disturbance while programming 有权
标题翻译：在编程时控制交流干扰
公开(公告)号：US08264898B2
公开(公告)日：2012-09-11
申请号：US13156763
申请日：2011-06-09
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

4. 发明申请

US20110235412A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
标题翻译：控制交流干扰编程
公开(公告)号：US20110235412A1
公开(公告)日：2011-09-29
申请号：US13156763
申请日：2011-06-09
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

5. 发明申请

US20100103732A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
标题翻译：控制交流干扰编程
公开(公告)号：US20100103732A1
公开(公告)日：2010-04-29
申请号：US12650118
申请日：2009-12-30
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

6. 发明授权

US07672803B1 Input of test conditions and output generation for built-in self test 有权
标题翻译：输入测试条件和输出产生内置自检
公开(公告)号：US07672803B1
公开(公告)日：2010-03-02
申请号：US11006034
申请日：2004-12-07
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R27/28
CPC分类号： G11C29/16 , G01R31/318511 , G11C16/04 , G11C29/12005 , G11C29/44
摘要： A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adjust the test conditions of the memory tests. The BIST interface circuit is operable to receive one or more global variables associated with the test conditions of a plurality of tests used on the flash memory and to output results of the memory tests based on the value of the variables. The global variables are used to adjust the test conditions and to trim one or more references used in various flash memory tests and operations. The system may further include a serial communications medium for communicating the global variables to the BIST interface and test results from the interface.
摘要翻译：讨论了一种用于为闪存器件的内置自测电路提供可编程测试条件的系统和方法。本发明采用具有用于测试存储器的BIST电路的闪速存储器和适于调整存储器测试的测试条件的BIST接口电路。 BIST接口电路可操作以接收与闪存上使用的多个测试的测试条件相关联的一个或多个全局变量，并且基于变量的值输出存储器测试的结果。全局变量用于调整测试条件并修剪用于各种闪存测试和操作的一个或多个引用。该系统还可以包括用于将全局变量传送到BIST接口的串行通信介质以及来自接口的测试结果。

7. 发明申请

US20090103357A1 FAST SINGLE PHASE PROGRAM ALGORITHM FOR QUADBIT 有权
标题翻译：用于四边形的快速单相程序算法
公开(公告)号：US20090103357A1
公开(公告)日：2009-04-23
申请号：US11874076
申请日：2007-10-17
申请人： Darlene Hamilton , Fatima Bathul , Kulachet Tanpairoj , Ou Li
发明人： Darlene Hamilton , Fatima Bathul , Kulachet Tanpairoj , Ou Li
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C2211/5621
摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.
摘要翻译：提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。学习元件对被编程以确定每个程序级的学习程序漏极电压。这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

8. 发明授权

US07130210B2 Multi-level ONO flash program algorithm for threshold width control 有权
公开(公告)号：US07130210B2
公开(公告)日：2006-10-31
申请号：US11034642
申请日：2005-01-13
申请人： Fatima Bathul , Darlene Hamilton , Masato Horiike
发明人： Fatima Bathul , Darlene Hamilton , Masato Horiike
IPC分类号： G11C17/00
CPC分类号： G11C16/16 , G11C11/5671
摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

9. 发明授权

US07206224B1 Methods and systems for high write performance in multi-bit flash memory devices 有权
公开(公告)号：US07206224B1
公开(公告)日：2007-04-17
申请号：US11037477
申请日：2005-01-18
申请人： Mark Randolph , Darlene Hamilton , Roni Kornitz
发明人： Mark Randolph , Darlene Hamilton , Roni Kornitz
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , G11C2211/5641
摘要： Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

10. 发明申请

US20070064464A1 High performance flash memory device capable of high density data storage 有权
标题翻译：高性能闪存设备能够进行高密度数据存储
公开(公告)号：US20070064464A1
公开(公告)日：2007-03-22
申请号：US11229527
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Le
发明人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Le
IPC分类号： G11C17/00
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。预定数量的位同时被编程到阵列中的对应存储器单元。同时验证阵列中预定位数的编程状态。

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