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    • 3. 发明授权
    • Erase method for a dual bit memory cell
    • 双位存储单元的擦除方法
    • US06901010B1
    • 2005-05-31
    • US10119366
    • 2002-04-08
    • Darlene G. HamiltonEric M. AjimineBinh LeEdward HsiaKen Tanpairoj
    • Darlene G. HamiltonEric M. AjimineBinh LeEdward HsiaKen Tanpairoj
    • G11C16/02G11C16/04G11C7/00
    • G11C16/107G11C16/0475G11C16/3409G11C16/3445G11C2216/18
    • An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.
    • 位于正常和互补位置的位的多位存储器阵列中的闪存单元的擦除方法。 执行正常位置中的位的擦除验证,并且如果正常位置中的位失败,并且如果还没有达到最大擦除脉冲计数,则将擦除脉冲施加到正常位和补充位。 执行补充位置中的位的擦除验证,并且如果补充位中的位失败,并且如果还没有达到最大擦除脉冲计数,则擦除脉冲将被施加到互补位和正常位位置。 如果这些位通过擦除验证,则这些位经过软编程验证。 如果这些位过高,并且如果没有达到软编程脉冲计数,则软编程脉冲将被施加到过高位。
    • 8. 发明申请
    • PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES
    • 使用浮动位线的非易失性存储器的部分速度和全速编程
    • US20110051517A1
    • 2011-03-03
    • US12547449
    • 2009-08-25
    • Man MuiYingda DongBinh LeDeepanshu Dutta
    • Man MuiYingda DongBinh LeDeepanshu Dutta
    • G11C16/04G11C16/06
    • G11C11/5628G11C16/0483G11C16/10G11C16/3418G11C16/3427
    • Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
    • 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间,在第一时间段中,要禁止的存储元件的位线被预充电,而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中,以部分速度编程的存储元件的位线被驱动得较高,而待禁止的存储元件的位线被浮置,并且待编程的存储元件的位线保持固定。 在第三时间段中,待被禁止的存储元件的位线被驱动得较高,而以部分速度或全速编程的存储元件的位线被浮动,使得它们耦合得更高。