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1. 发明授权

US08288293B2 Integrated circuit fabrication using sidewall nitridation processes 有权
标题翻译：使用侧壁氮化工艺的集成电路制造
公开(公告)号：US08288293B2
公开(公告)日：2012-10-16
申请号：US12763963
申请日：2010-04-20
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L21/469
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

2. 发明申请

US20100270608A1 Integrated Circuits And Fabrication Using Sidewall Nitridation Processes 有权
标题翻译：集成电路和使用侧壁氮化工艺的制造
公开(公告)号：US20100270608A1
公开(公告)日：2010-10-28
申请号：US12763963
申请日：2010-04-20
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/792 , H01L21/28 , H01L21/76
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

3. 发明申请

US20060152974A1 Multi-level ONO flash program algorithm for threshold width control 有权
公开(公告)号：US20060152974A1
公开(公告)日：2006-07-13
申请号：US11034642
申请日：2005-01-13
申请人： Fatima Bathul , Darlene Hamilton , Masato Horiike
发明人： Fatima Bathul , Darlene Hamilton , Masato Horiike
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C11/5671
摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough. Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

4. 发明申请

US20050276120A1 Erase algorithm for multi-level bit flash memory 有权
标题翻译：多级位闪存的擦除算法
公开(公告)号：US20050276120A1
公开(公告)日：2005-12-15
申请号：US10864947
申请日：2004-06-10
申请人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
发明人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
IPC分类号： G11C11/56 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3413 , G11C11/5635 , G11C16/3404 , G11C16/3409
摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.
摘要翻译：提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到对应于单元的期望的最终阈值电压值的最终数据状态。可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

5. 发明授权

US07251158B2 Erase algorithm for multi-level bit flash memory 有权
标题翻译：多级位闪存的擦除算法
公开(公告)号：US07251158B2
公开(公告)日：2007-07-31
申请号：US10864947
申请日：2004-06-10
申请人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
发明人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
IPC分类号： G11C11/34
CPC分类号： G11C16/3413 , G11C11/5635 , G11C16/3404 , G11C16/3409
摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.
摘要翻译：提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到与单元的期望的最终阈值电压值对应的最终数据状态。可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

6. 发明授权

US08853763B2 Integrated circuits with sidewall nitridation 有权
标题翻译：具有侧壁氮化的集成电路
公开(公告)号：US08853763B2
公开(公告)日：2014-10-07
申请号：US13607375
申请日：2012-09-07
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/76 , H01L27/115 , H01L29/66 , H01L21/28
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

7. 发明申请

US20120326220A1 Integrated Circuits With Sidewall Nitridation 有权
标题翻译：集成电路与侧壁氮化
公开(公告)号：US20120326220A1
公开(公告)日：2012-12-27
申请号：US13607375
申请日：2012-09-07
申请人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
发明人： Tuan Pham , Sanghyun Lee , Masato Horiike , Klaus Schuegraf , Masaaki Higashitani , Keiichi Isono
IPC分类号： H01L29/78
CPC分类号： H01L27/11548 , H01L21/2815 , H01L27/11529 , H01L29/66825
摘要： Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.
摘要翻译：半导体器件设置有用于在制造工艺期间保护侧壁特征的封装膜，例如蚀刻以形成隔离区域。在非易失性闪速存储器中，例如，沟槽隔离工艺被分成段以沿着电荷存储材料的侧壁并入封装膜。在层堆叠上形成图案，随后蚀刻电荷存储材料，以形成沿着衬底的列方向延伸的条带，其间具有隧道介电材料层。在蚀刻基板之前，沿着电荷存储材料条的侧壁形成封装膜。封装膜可以在随后的清洁，氧化和蚀刻工艺期间保护电荷存储材料的侧壁。在另一个实例中，同时形成封装膜，同时蚀刻以形成电荷存储材料条和隔离槽。

8. 发明授权

US07038948B2 Read approach for multi-level virtual ground memory 有权
标题翻译：多级虚拟接地存储器的读取方法
公开(公告)号：US07038948B2
公开(公告)日：2006-05-02
申请号：US10946809
申请日：2004-09-22
申请人： Darlene Hamilton , Fatima Bathul , Masato Horiike , Eugen Gershon , Michael Van Buskirk
发明人： Darlene Hamilton , Fatima Bathul , Masato Horiike , Eugen Gershon , Michael Van Buskirk
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/34 , G11C16/3418 , G11C2211/5634
摘要： The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.
摘要翻译：本发明涉及用于确定双面ONO闪速存储器单元中的位的电平的技术，其中双面ONO闪存单元的每个位可以被编程为多个电平。本发明的一个或多个方面考虑到一位上的电荷电平对另一位可能具有的影响，或称为互补位干扰的影响。被称为跨导的度量被用于使位电平确定提供更大程度的分辨率和精度。以这种方式，根据本发明的一个或多个方面确定比特级别减轻了错误或错误的读取。

9. 发明申请

US20060062054A1 READ APPROACH FOR MULTI-LEVEL VIRTUAL GROUND MEMORY 有权
标题翻译：多级虚拟接地存储器的阅读方法
公开(公告)号：US20060062054A1
公开(公告)日：2006-03-23
申请号：US10946809
申请日：2004-09-22
申请人： Darlene Hamilton , Fatima Bathul , Masato Horiike , Eugen Gershon , Michael Buskirk
发明人： Darlene Hamilton , Fatima Bathul , Masato Horiike , Eugen Gershon , Michael Buskirk
IPC分类号： G11C7/06 , G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/34 , G11C16/3418 , G11C2211/5634
摘要： The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.
摘要翻译：本发明涉及用于确定双面ONO闪速存储器单元中的位的电平的技术，其中双面ONO闪存单元的每个位可以被编程为多个电平。本发明的一个或多个方面考虑到一位上的电荷电平对另一位可能具有的影响，或称为互补位干扰的影响。被称为跨导的度量被用于使位电平确定提供更大程度的分辨率和精度。以这种方式，根据本发明的一个或多个方面确定比特级别减轻了错误或错误的读取。

10. 发明授权

US07130210B2 Multi-level ONO flash program algorithm for threshold width control 有权
公开(公告)号：US07130210B2
公开(公告)日：2006-10-31
申请号：US11034642
申请日：2005-01-13
申请人： Fatima Bathul , Darlene Hamilton , Masato Horiike
发明人： Fatima Bathul , Darlene Hamilton , Masato Horiike
IPC分类号： G11C17/00
CPC分类号： G11C16/16 , G11C11/5671
摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

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