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1. 发明授权

US06184142B2 Process for low k organic dielectric film etch 有权
标题翻译：低k有机介质膜蚀刻工艺
公开(公告)号：US06184142B2
公开(公告)日：2001-02-06
申请号：US09302204
申请日：1999-04-26
申请人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： H01L2100
CPC分类号： H01L21/76807 , H01L21/31144 , H01L21/76802
摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.
摘要翻译：公开了一种用于蚀刻低k有机介电膜的简化方法。衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

2. 发明授权

US6159845A Method for manufacturing dielectric layer 有权
标题翻译：电介质层制造方法
公开(公告)号：US6159845A
公开(公告)日：2000-12-12
申请号：US395906
申请日：1999-09-11
申请人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
发明人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7681 , H01L21/7682 , H01L21/7684 , H01L21/76885
摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
摘要翻译：描述双镶嵌互连中的电介质层。在基板上形成双镶嵌互连结构。所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。第二线穿透第二电介质层并且电耦合到衬底。去除第二介电层。保护层形成在衬底上。第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。在第三电介质层上形成第四电介质层。执行平面化处理以平坦化第四介电层。

3. 发明授权

US6017817A Method of fabricating dual damascene 有权
标题翻译：双镶嵌方法
公开(公告)号：US6017817A
公开(公告)日：2000-01-25
申请号：US309186
申请日：1999-05-10
申请人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
发明人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76807
摘要： A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.
摘要翻译：一种制造双镶嵌结构的方法。在具有有源区的基板上依次形成低k电介质层和盖层。在盖层上形成第一光致抗蚀剂层，然后对盖层进行图案化以暴露低k电介质层的一部分。同时去除第一光致抗蚀剂层和低k电介质层的一部分以形成布线开口。在盖层上形成第二光致抗蚀剂层以覆盖布线开口的一部分。当执行去除第二光致抗蚀剂层的步骤时，形成通孔，以通过同时去除暴露的低k电介质层来暴露有源区。通孔和布线开口填充有金属层以形成布线和通孔。

4. 发明授权

US06254676B1 Method for manufacturing metal oxide semiconductor transistor having raised source/drain 有权
标题翻译：制造具有升高的源极/漏极的金属氧化物半导体晶体管的方法
公开(公告)号：US06254676B1
公开(公告)日：2001-07-03
申请号：US09340969
申请日：1999-06-28
申请人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
发明人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
IPC分类号： C30B2514
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66628 , Y10S438/981
摘要： A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
摘要翻译：描述了具有升高的源极/漏极的金属氧化物半导体晶体管的制造方法。在栅电极的侧壁上形成第一间隔物。然后在衬底的暴露表面和栅电极的顶表面上形成外延层。然后在使用栅电极和第一间隔件作为第一掩模的同时在衬底上执行光注入步骤。此后，在栅电极的侧壁上形成第二间隔物。然后在使用栅电极，第一间隔物和第二间隔物作为第二掩模的同时在衬底上执行沉重的注入步骤。然后在形成源极/漏极的延伸结构之前形成外延层。因此，源/漏扩展结构中的掺杂剂避免了形成外延层所需的高温，从而防止掺杂剂的再分布。

5. 发明授权

US06361929B1 Method of removing a photo-resist layer on a semiconductor wafer 有权
标题翻译：去除半导体晶片上的光致抗蚀剂层的方法
公开(公告)号：US06361929B1
公开(公告)日：2002-03-26
申请号：US09373755
申请日：1999-08-13
申请人： Hsein-Ta Chung , Yi-Yu Hsu , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsein-Ta Chung , Yi-Yu Hsu , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： G03F736
CPC分类号： G03F7/427 , G03F7/42
摘要： The present invention relates to a method of removing a photo-resist layer from a semiconductor wafer. The semiconductor wafer comprises an inter-metal dielectric layer (IMD), and a photo-resist layer positioned on the IMD. The method comprises performing a dry cleaning process by injecting a nitrogen-containing gas into an oxygen-free environment and utilizing a plasma reaction to remove most of the photo-resist layer, and performing a wet cleaning process to completely remove the photo-resist layer.
摘要翻译：本发明涉及从半导体晶片去除光致抗蚀剂层的方法。半导体晶片包括金属间介电层（IMD）和位于IMD上的光致抗蚀剂层。该方法包括通过将含氮气体注入无氧环境并利用等离子体反应去除大部分光致抗蚀剂层进行干洗处理，并进行湿式清洗处理以完全除去光致抗蚀剂层。

6. 发明授权

US08937241B2 Self-assembly nano-composite solar cell 有权
标题翻译：自组装纳米复合太阳能电池
公开(公告)号：US08937241B2
公开(公告)日：2015-01-20
申请号：US13458272
申请日：2012-04-27
申请人： Che-Ning Yeh , Chun-Te Ho , Tri-Rung Yew
发明人： Che-Ning Yeh , Chun-Te Ho , Tri-Rung Yew
IPC分类号： H01L31/042 , H01L31/0384 , H01L31/0376 , H01L31/0352
CPC分类号： H01L31/03845 , B82Y30/00 , H01L31/035227 , H01L31/035281 , H01L31/03767 , H01L31/075 , H01L31/1804 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： A self-assembly nano-composite solar cell comprises a substrate, a first electrode layer, a composite absorption layer and a second electrode layer. The first electrode layer is formed on the substrate. The composite absorption layer is formed over the first electrode layer and includes a plurality of vertical nano-pillars, a plurality of gaps each formed between any two adjacent nano-pillars, and a plurality of bismuth sulfide nano-particles filled into the gaps and attached to the nano-pillars. The second electrode layer is formed over the composite absorption layer. Through etching and soaking in solutions, the composite absorption layer with nano-pillars and bismuth sulfide nano-particles is fabricated to form a self-assembly nano-composite solar cell having high power conversion efficiency.
摘要翻译：自组装纳米复合太阳能电池包括基板，第一电极层，复合吸收层和第二电极层。第一电极层形成在基板上。复合吸收层形成在第一电极层之上，并且包括多个垂直纳米柱，在任何两个相邻的纳米柱之间形成的多个间隙和填充到间隙中的多个硫化铋纳米颗粒到纳米柱。第二电极层形成在复合吸收层上。通过蚀刻和浸泡在溶液中，制备具有纳米柱和硫化铋纳米颗粒的复合吸收层，以形成具有高功率转换效率的自组装纳米复合太阳能电池。

7. 发明申请

US20110144471A1 FLEXIBLE PROBE STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：柔性探针结构及其制造方法
公开(公告)号：US20110144471A1
公开(公告)日：2011-06-16
申请号：US12639605
申请日：2009-12-16
申请人： Hui-Lin HSU , Tri-Rung Yew , Hsin Chen , Yung-Chan Chen
发明人： Hui-Lin HSU , Tri-Rung Yew , Hsin Chen , Yung-Chan Chen
IPC分类号： A61B5/0478 , H05K3/10
CPC分类号： A61B5/0478 , A61B5/4058 , A61B5/4824 , A61B5/6846 , A61B2562/125 , B82Y15/00 , B82Y30/00 , H05K1/0393 , H05K3/24 , H05K2201/026 , H05K2201/0323 , Y10T29/49155
摘要： The present invention discloses a flexible probe structure comprises at least one electrode using a CNT layer as the electrode interface. The CNT layer disposed on the electrode surface is processed with an UV-ozone treatment to form a great number of carbon-oxygen functional groups on the surface of CNT. The carbon-oxygen functional groups can greatly reduce the interface impedance of the electrode and the biological tissue fluid. Thereby, the measurement can achieve better quality. The present invention also discloses a method for fabricating a flexible probe structure, which comprises steps: preparing a flexible substrate; forming a conductive layer on the flexible substrate, and defining an electrode, a wire and a metal pad on the conductive layer; forming a CNT layer on the electrode; forming an insulating layer on the conductive layer to insulate the wire from the environment; and processing the CNT layer with an UV-ozone treatment.
摘要翻译：本发明公开了一种柔性探针结构，其包括使用CNT层作为电极界面的至少一个电极。通过UV-臭氧处理处理设置在电极表面上的CNT层，以在CNT的表面上形成大量的碳 - 氧官能团。碳氧官能团可以大大降低电极和生物组织液的界面阻抗。因此，测量可以实现更好的质量。本发明还公开了一种用于制造柔性探针结构的方法，其包括步骤：制备柔性基底; 在所述柔性基板上形成导电层，并且在所述导电层上限定电极，导线和金属焊盘; 在所述电极上形成CNT层; 在导电层上形成绝缘层以使电线与环境绝缘; 并用UV-臭氧处理处理CNT层。

8. 发明申请

US20090250731A1 Field-effect transistor structure and fabrication method thereof 审中-公开
公开(公告)号：US20090250731A1
公开(公告)日：2009-10-08
申请号：US12080505
申请日：2008-04-02
申请人： Tsung-Yeh Yang , Tri-Rung Yew
发明人： Tsung-Yeh Yang , Tri-Rung Yew
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0545
摘要： A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer, and contain nickel and chromium. The CNT is disposed on the dielectric layer and electrically connects two conductive electrodes

9. 发明申请

US20090236675A1 SELF-ALIGNED FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：自对准场效应晶体管结构及其制造方法
公开(公告)号：US20090236675A1
公开(公告)日：2009-09-24
申请号：US12052738
申请日：2008-03-21
申请人： Wei-Chang Yang , Tri-Rung Yew
发明人： Wei-Chang Yang , Tri-Rung Yew
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0002 , H01L51/0545 , H01L51/105
摘要： A self-aligned field-effect transistor (FET) is provided. The self-aligned FET includes a substrate, a dielectric layer, conductive electrodes, and a carbon nanotube. A patterned back-gated conductive electrode is disposed in the substrate. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer and function as a source/drain. The patterned source/drain conductive electrodes contain a metal silicide such as cobalt silicide serve as a catalyst for carbon nanotube synthesis. The carbon nanotube is disposed on the dielectric layer to be electrically connected with the source/drain conductive electrodes.
摘要翻译：提供了自对准场效应晶体管（FET）。自对准FET包括基板，电介质层，导电电极和碳纳米管。图案化的背栅导电电极设置在基板中。电介质层设置在基板上。导电电极设置在电介质层上并用作源极/漏极。图案化的源极/漏极导电电极包含金属硅化物，例如钴硅化物，用作碳纳米管合成的催化剂。碳纳米管设置在与源极/漏极导电电极电连接的电介质层上。

10. 发明申请

US20090197113A1 Interconnect structure and method of fabricating the same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20090197113A1
公开(公告)日：2009-08-06
申请号：US12229233
申请日：2008-08-20
申请人： Yu-Tsung Wu , Jen-Hong Huang , Chung-Min Tsai , Huan-Chieh Su , Tri-Rung Yew
发明人： Yu-Tsung Wu , Jen-Hong Huang , Chung-Min Tsai , Huan-Chieh Su , Tri-Rung Yew
IPC分类号： H01L21/70
CPC分类号： H01L21/76823 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10T428/12625 , Y10T428/24851 , H01L2924/00
摘要： A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.
摘要翻译：描述制造互连结构的方法。提供基板。在基板上形成有图案的界面金属层。形成覆盖基板和界面金属层的无定形碳绝缘层或碳基绝缘层。在与界面金属层电连接的无定形碳或碳基绝缘层中形成导电碳线或插塞。还描述了一种互连结构，包括衬底，衬底上的图案化界面金属层，衬底上的无定形碳绝缘层或碳基绝缘层，以及设置在无定形碳或碳中的导电碳线或插塞的绝缘层，并与界面金属层电连接。

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