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    • 2. 发明授权
    • Method for manufacturing dielectric layer
    • 电介质层制造方法
    • US6159845A
    • 2000-12-12
    • US395906
    • 1999-09-11
    • Tri-Rung YewWater LurHsien-Ta Chung
    • Tri-Rung YewWater LurHsien-Ta Chung
    • H01L21/768H01L21/4763
    • H01L21/76834H01L21/7681H01L21/7682H01L21/7684H01L21/76885
    • A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
    • 描述双镶嵌互连中的电介质层。 在基板上形成双镶嵌互连结构。 所述双镶嵌互连结构具有形成在所述基板上的第一电介质层,形成在所述第一电介质层上的第二电介质层,穿过所述第二电介质层的第一电线和第二导线。 第二线穿透第二电介质层并且电耦合到衬底。 去除第二介电层。 保护层形成在衬底上。 第三电介质层形成在阻挡盖层上,并且在由第三电介质层,第一和第二电线围绕的空间中形成气隙。 在第三电介质层上形成第四电介质层。 执行平面化处理以平坦化第四介电层。
    • 3. 发明授权
    • Method of fabricating dual damascene
    • 双镶嵌方法
    • US6017817A
    • 2000-01-25
    • US309186
    • 1999-05-10
    • Hsien-Ta ChungTri-Rung YewWater Lur
    • Hsien-Ta ChungTri-Rung YewWater Lur
    • H01L21/768H01L21/4763H01L21/311
    • H01L21/76807
    • A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.
    • 一种制造双镶嵌结构的方法。 在具有有源区的基板上依次形成低k电介质层和盖层。 在盖层上形成第一光致抗蚀剂层,然后对盖层进行图案化以暴露低k电介质层的一部分。 同时去除第一光致抗蚀剂层和低k电介质层的一部分以形成布线开口。 在盖层上形成第二光致抗蚀剂层以覆盖布线开口的一部分。 当执行去除第二光致抗蚀剂层的步骤时,形成通孔,以通过同时去除暴露的低k电介质层来暴露有源区。 通孔和布线开口填充有金属层以形成布线和通孔。