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1. 发明授权

US6159845A Method for manufacturing dielectric layer 有权
标题翻译：电介质层制造方法
公开(公告)号：US6159845A
公开(公告)日：2000-12-12
申请号：US395906
申请日：1999-09-11
申请人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
发明人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7681 , H01L21/7682 , H01L21/7684 , H01L21/76885
摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
摘要翻译：描述双镶嵌互连中的电介质层。在基板上形成双镶嵌互连结构。所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。第二线穿透第二电介质层并且电耦合到衬底。去除第二介电层。保护层形成在衬底上。第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。在第三电介质层上形成第四电介质层。执行平面化处理以平坦化第四介电层。

2. 发明授权

US6017817A Method of fabricating dual damascene 有权
标题翻译：双镶嵌方法
公开(公告)号：US6017817A
公开(公告)日：2000-01-25
申请号：US309186
申请日：1999-05-10
申请人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
发明人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76807
摘要： A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.
摘要翻译：一种制造双镶嵌结构的方法。在具有有源区的基板上依次形成低k电介质层和盖层。在盖层上形成第一光致抗蚀剂层，然后对盖层进行图案化以暴露低k电介质层的一部分。同时去除第一光致抗蚀剂层和低k电介质层的一部分以形成布线开口。在盖层上形成第二光致抗蚀剂层以覆盖布线开口的一部分。当执行去除第二光致抗蚀剂层的步骤时，形成通孔，以通过同时去除暴露的低k电介质层来暴露有源区。通孔和布线开口填充有金属层以形成布线和通孔。

3. 发明授权

US06254676B1 Method for manufacturing metal oxide semiconductor transistor having raised source/drain 有权
标题翻译：制造具有升高的源极/漏极的金属氧化物半导体晶体管的方法
公开(公告)号：US06254676B1
公开(公告)日：2001-07-03
申请号：US09340969
申请日：1999-06-28
申请人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
发明人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
IPC分类号： C30B2514
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66628 , Y10S438/981
摘要： A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
摘要翻译：描述了具有升高的源极/漏极的金属氧化物半导体晶体管的制造方法。在栅电极的侧壁上形成第一间隔物。然后在衬底的暴露表面和栅电极的顶表面上形成外延层。然后在使用栅电极和第一间隔件作为第一掩模的同时在衬底上执行光注入步骤。此后，在栅电极的侧壁上形成第二间隔物。然后在使用栅电极，第一间隔物和第二间隔物作为第二掩模的同时在衬底上执行沉重的注入步骤。然后在形成源极/漏极的延伸结构之前形成外延层。因此，源/漏扩展结构中的掺杂剂避免了形成外延层所需的高温，从而防止掺杂剂的再分布。

4. 发明授权

US06184142B2 Process for low k organic dielectric film etch 有权
标题翻译：低k有机介质膜蚀刻工艺
公开(公告)号：US06184142B2
公开(公告)日：2001-02-06
申请号：US09302204
申请日：1999-04-26
申请人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： H01L2100
CPC分类号： H01L21/76807 , H01L21/31144 , H01L21/76802
摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.
摘要翻译：公开了一种用于蚀刻低k有机介电膜的简化方法。衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

5. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

6. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

7. 发明授权

US6020258A Method for unlanded via etching using etch stop 失效
标题翻译：使用蚀刻停止法进行无衬底通孔蚀刻的方法
公开(公告)号：US6020258A
公开(公告)日：2000-02-01
申请号：US982266
申请日：1997-12-01
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76834 , Y10S438/97
摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.
摘要翻译：形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。在层间电介质的表面上设置一级布线。第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。

8. 发明授权

US5960299A Method of fabricating a shallow-trench isolation structure in integrated circuit 失效
标题翻译：在集成电路中制造浅沟槽隔离结构的方法
公开(公告)号：US5960299A
公开(公告)日：1999-09-28
申请号：US181466
申请日：1998-10-28
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.
摘要翻译：提供了一种用于在集成电路中制造浅沟槽隔离（STI）结构的半导体制造方法，其可以防止在STI结构的氧化物塞中发生微细纹理，从而进一步防止桥接效应的发生，要通过STI结构电隔离的电路元件之间的电路。该方法的特征在于使用激光退火工艺来除去在用于去除氧化物层的上部以形成氧化物的化学机械抛光（CMP）工艺期间在氧化物塞的顶表面上形成的微观尺度堵塞该方法因此可以防止桥接效应的发生和由于形成在现有技术中将会出现的微纹理造成的短路。

9. 发明授权

US06251783B1 Method of manufacturing shallow trench isolation 失效
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US06251783B1
公开(公告)日：2001-06-26
申请号：US09189847
申请日：1998-11-12
申请人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.
摘要翻译：制造浅沟槽隔离结构的方法。该方法包括以下步骤：将绝缘材料沉积到衬底的沟槽中以形成绝缘层。基板具有多个活性区域，每个活性区域占据不同的区域并且具有不同的尺寸。此外，在每个有源区的顶部有一个氮化硅层。此后，然后将光致抗蚀剂层沉积在绝缘层上。接下来，将光致抗蚀剂层的一部分回蚀刻以暴露氧化物层的一部分，使得剩余的光致抗蚀剂材料在绝缘层的凹陷区域上形成覆盖层。随后，使用光致抗蚀剂覆盖层作为掩模，蚀刻绝缘层以去除暴露的氧化物层的一部分，从而在氧化物层内形成沟槽。之后，去除光致抗蚀剂覆盖层。最后，进行化学机械抛光操作以抛光绝缘层，直到暴露氮化硅层。

10. 发明授权

US06251769B1 Method of manufacturing contact pad 失效
标题翻译：制造接触垫的方法
公开(公告)号：US06251769B1
公开(公告)日：2001-06-26
申请号：US09347180
申请日：1999-07-02
申请人： Tri-Rung Yew , Kuo-Tai Huang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Water Lur
IPC分类号： H01L214763
CPC分类号： H01L24/03 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76814 , H01L21/76879 , H01L21/76895 , H01L21/76897 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.
摘要翻译：一种制造接触垫的方法。提供其中形成有源极/漏极区的衬底。介电层形成在衬底上。在电介质层中形成开口并使源极/漏极区域露出。执行选择性外延工艺以在开口中形成接触焊盘，其中接触焊盘的顶部延伸到介电层的表面上。

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