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1. 发明授权

US6159845A Method for manufacturing dielectric layer 有权
标题翻译：电介质层制造方法
公开(公告)号：US6159845A
公开(公告)日：2000-12-12
申请号：US395906
申请日：1999-09-11
申请人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
发明人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7681 , H01L21/7682 , H01L21/7684 , H01L21/76885
摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
摘要翻译：描述双镶嵌互连中的电介质层。在基板上形成双镶嵌互连结构。所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。第二线穿透第二电介质层并且电耦合到衬底。去除第二介电层。保护层形成在衬底上。第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。在第三电介质层上形成第四电介质层。执行平面化处理以平坦化第四介电层。

2. 发明授权

US6017817A Method of fabricating dual damascene 有权
标题翻译：双镶嵌方法
公开(公告)号：US6017817A
公开(公告)日：2000-01-25
申请号：US309186
申请日：1999-05-10
申请人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
发明人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76807
摘要： A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.
摘要翻译：一种制造双镶嵌结构的方法。在具有有源区的基板上依次形成低k电介质层和盖层。在盖层上形成第一光致抗蚀剂层，然后对盖层进行图案化以暴露低k电介质层的一部分。同时去除第一光致抗蚀剂层和低k电介质层的一部分以形成布线开口。在盖层上形成第二光致抗蚀剂层以覆盖布线开口的一部分。当执行去除第二光致抗蚀剂层的步骤时，形成通孔，以通过同时去除暴露的低k电介质层来暴露有源区。通孔和布线开口填充有金属层以形成布线和通孔。

3. 发明授权

US06184142B2 Process for low k organic dielectric film etch 有权
标题翻译：低k有机介质膜蚀刻工艺
公开(公告)号：US06184142B2
公开(公告)日：2001-02-06
申请号：US09302204
申请日：1999-04-26
申请人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： H01L2100
CPC分类号： H01L21/76807 , H01L21/31144 , H01L21/76802
摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.
摘要翻译：公开了一种用于蚀刻低k有机介电膜的简化方法。衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

4. 发明授权

US06254676B1 Method for manufacturing metal oxide semiconductor transistor having raised source/drain 有权
标题翻译：制造具有升高的源极/漏极的金属氧化物半导体晶体管的方法
公开(公告)号：US06254676B1
公开(公告)日：2001-07-03
申请号：US09340969
申请日：1999-06-28
申请人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
发明人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
IPC分类号： C30B2514
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66628 , Y10S438/981
摘要： A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
摘要翻译：描述了具有升高的源极/漏极的金属氧化物半导体晶体管的制造方法。在栅电极的侧壁上形成第一间隔物。然后在衬底的暴露表面和栅电极的顶表面上形成外延层。然后在使用栅电极和第一间隔件作为第一掩模的同时在衬底上执行光注入步骤。此后，在栅电极的侧壁上形成第二间隔物。然后在使用栅电极，第一间隔物和第二间隔物作为第二掩模的同时在衬底上执行沉重的注入步骤。然后在形成源极/漏极的延伸结构之前形成外延层。因此，源/漏扩展结构中的掺杂剂避免了形成外延层所需的高温，从而防止掺杂剂的再分布。

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