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1. 发明授权

US06361929B1 Method of removing a photo-resist layer on a semiconductor wafer 有权
标题翻译：去除半导体晶片上的光致抗蚀剂层的方法
公开(公告)号：US06361929B1
公开(公告)日：2002-03-26
申请号：US09373755
申请日：1999-08-13
申请人： Hsein-Ta Chung , Yi-Yu Hsu , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsein-Ta Chung , Yi-Yu Hsu , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： G03F736
CPC分类号： G03F7/427 , G03F7/42
摘要： The present invention relates to a method of removing a photo-resist layer from a semiconductor wafer. The semiconductor wafer comprises an inter-metal dielectric layer (IMD), and a photo-resist layer positioned on the IMD. The method comprises performing a dry cleaning process by injecting a nitrogen-containing gas into an oxygen-free environment and utilizing a plasma reaction to remove most of the photo-resist layer, and performing a wet cleaning process to completely remove the photo-resist layer.
摘要翻译：本发明涉及从半导体晶片去除光致抗蚀剂层的方法。半导体晶片包括金属间介电层（IMD）和位于IMD上的光致抗蚀剂层。该方法包括通过将含氮气体注入无氧环境并利用等离子体反应去除大部分光致抗蚀剂层进行干洗处理，并进行湿式清洗处理以完全除去光致抗蚀剂层。

2. 发明授权

US06184142B2 Process for low k organic dielectric film etch 有权
标题翻译：低k有机介质膜蚀刻工艺
公开(公告)号：US06184142B2
公开(公告)日：2001-02-06
申请号：US09302204
申请日：1999-04-26
申请人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsien-Ta Chung , Chan-Lon Yang , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： H01L2100
CPC分类号： H01L21/76807 , H01L21/31144 , H01L21/76802
摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.
摘要翻译：公开了一种用于蚀刻低k有机介电膜的简化方法。衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

3. 发明授权

US08937241B2 Self-assembly nano-composite solar cell 有权
标题翻译：自组装纳米复合太阳能电池
公开(公告)号：US08937241B2
公开(公告)日：2015-01-20
申请号：US13458272
申请日：2012-04-27
申请人： Che-Ning Yeh , Chun-Te Ho , Tri-Rung Yew
发明人： Che-Ning Yeh , Chun-Te Ho , Tri-Rung Yew
IPC分类号： H01L31/042 , H01L31/0384 , H01L31/0376 , H01L31/0352
CPC分类号： H01L31/03845 , B82Y30/00 , H01L31/035227 , H01L31/035281 , H01L31/03767 , H01L31/075 , H01L31/1804 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： A self-assembly nano-composite solar cell comprises a substrate, a first electrode layer, a composite absorption layer and a second electrode layer. The first electrode layer is formed on the substrate. The composite absorption layer is formed over the first electrode layer and includes a plurality of vertical nano-pillars, a plurality of gaps each formed between any two adjacent nano-pillars, and a plurality of bismuth sulfide nano-particles filled into the gaps and attached to the nano-pillars. The second electrode layer is formed over the composite absorption layer. Through etching and soaking in solutions, the composite absorption layer with nano-pillars and bismuth sulfide nano-particles is fabricated to form a self-assembly nano-composite solar cell having high power conversion efficiency.
摘要翻译：自组装纳米复合太阳能电池包括基板，第一电极层，复合吸收层和第二电极层。第一电极层形成在基板上。复合吸收层形成在第一电极层之上，并且包括多个垂直纳米柱，在任何两个相邻的纳米柱之间形成的多个间隙和填充到间隙中的多个硫化铋纳米颗粒到纳米柱。第二电极层形成在复合吸收层上。通过蚀刻和浸泡在溶液中，制备具有纳米柱和硫化铋纳米颗粒的复合吸收层，以形成具有高功率转换效率的自组装纳米复合太阳能电池。

4. 发明申请

US20110144471A1 FLEXIBLE PROBE STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：柔性探针结构及其制造方法
公开(公告)号：US20110144471A1
公开(公告)日：2011-06-16
申请号：US12639605
申请日：2009-12-16
申请人： Hui-Lin HSU , Tri-Rung Yew , Hsin Chen , Yung-Chan Chen
发明人： Hui-Lin HSU , Tri-Rung Yew , Hsin Chen , Yung-Chan Chen
IPC分类号： A61B5/0478 , H05K3/10
CPC分类号： A61B5/0478 , A61B5/4058 , A61B5/4824 , A61B5/6846 , A61B2562/125 , B82Y15/00 , B82Y30/00 , H05K1/0393 , H05K3/24 , H05K2201/026 , H05K2201/0323 , Y10T29/49155
摘要： The present invention discloses a flexible probe structure comprises at least one electrode using a CNT layer as the electrode interface. The CNT layer disposed on the electrode surface is processed with an UV-ozone treatment to form a great number of carbon-oxygen functional groups on the surface of CNT. The carbon-oxygen functional groups can greatly reduce the interface impedance of the electrode and the biological tissue fluid. Thereby, the measurement can achieve better quality. The present invention also discloses a method for fabricating a flexible probe structure, which comprises steps: preparing a flexible substrate; forming a conductive layer on the flexible substrate, and defining an electrode, a wire and a metal pad on the conductive layer; forming a CNT layer on the electrode; forming an insulating layer on the conductive layer to insulate the wire from the environment; and processing the CNT layer with an UV-ozone treatment.
摘要翻译：本发明公开了一种柔性探针结构，其包括使用CNT层作为电极界面的至少一个电极。通过UV-臭氧处理处理设置在电极表面上的CNT层，以在CNT的表面上形成大量的碳 - 氧官能团。碳氧官能团可以大大降低电极和生物组织液的界面阻抗。因此，测量可以实现更好的质量。本发明还公开了一种用于制造柔性探针结构的方法，其包括步骤：制备柔性基底; 在所述柔性基板上形成导电层，并且在所述导电层上限定电极，导线和金属焊盘; 在所述电极上形成CNT层; 在导电层上形成绝缘层以使电线与环境绝缘; 并用UV-臭氧处理处理CNT层。

5. 发明申请

US20090250731A1 Field-effect transistor structure and fabrication method thereof 审中-公开
公开(公告)号：US20090250731A1
公开(公告)日：2009-10-08
申请号：US12080505
申请日：2008-04-02
申请人： Tsung-Yeh Yang , Tri-Rung Yew
发明人： Tsung-Yeh Yang , Tri-Rung Yew
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0545
摘要： A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer, and contain nickel and chromium. The CNT is disposed on the dielectric layer and electrically connects two conductive electrodes

6. 发明申请

US20090236675A1 SELF-ALIGNED FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：自对准场效应晶体管结构及其制造方法
公开(公告)号：US20090236675A1
公开(公告)日：2009-09-24
申请号：US12052738
申请日：2008-03-21
申请人： Wei-Chang Yang , Tri-Rung Yew
发明人： Wei-Chang Yang , Tri-Rung Yew
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0002 , H01L51/0545 , H01L51/105
摘要： A self-aligned field-effect transistor (FET) is provided. The self-aligned FET includes a substrate, a dielectric layer, conductive electrodes, and a carbon nanotube. A patterned back-gated conductive electrode is disposed in the substrate. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer and function as a source/drain. The patterned source/drain conductive electrodes contain a metal silicide such as cobalt silicide serve as a catalyst for carbon nanotube synthesis. The carbon nanotube is disposed on the dielectric layer to be electrically connected with the source/drain conductive electrodes.
摘要翻译：提供了自对准场效应晶体管（FET）。自对准FET包括基板，电介质层，导电电极和碳纳米管。图案化的背栅导电电极设置在基板中。电介质层设置在基板上。导电电极设置在电介质层上并用作源极/漏极。图案化的源极/漏极导电电极包含金属硅化物，例如钴硅化物，用作碳纳米管合成的催化剂。碳纳米管设置在与源极/漏极导电电极电连接的电介质层上。

7. 发明申请

US20090197113A1 Interconnect structure and method of fabricating the same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20090197113A1
公开(公告)日：2009-08-06
申请号：US12229233
申请日：2008-08-20
申请人： Yu-Tsung Wu , Jen-Hong Huang , Chung-Min Tsai , Huan-Chieh Su , Tri-Rung Yew
发明人： Yu-Tsung Wu , Jen-Hong Huang , Chung-Min Tsai , Huan-Chieh Su , Tri-Rung Yew
IPC分类号： H01L21/70
CPC分类号： H01L21/76823 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10T428/12625 , Y10T428/24851 , H01L2924/00
摘要： A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.
摘要翻译：描述制造互连结构的方法。提供基板。在基板上形成有图案的界面金属层。形成覆盖基板和界面金属层的无定形碳绝缘层或碳基绝缘层。在与界面金属层电连接的无定形碳或碳基绝缘层中形成导电碳线或插塞。还描述了一种互连结构，包括衬底，衬底上的图案化界面金属层，衬底上的无定形碳绝缘层或碳基绝缘层，以及设置在无定形碳或碳中的导电碳线或插塞的绝缘层，并与界面金属层电连接。

8. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

9. 发明授权

US06680248B2 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06680248B2
公开(公告)日：2004-01-20
申请号：US09991131
申请日：2001-11-20
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76807
摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.
摘要翻译：形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。沟槽和第一开口一起形成双镶嵌结构的开口。最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

10. 发明授权

US06479344B2 Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US06479344B2
公开(公告)日：2002-11-12
申请号：US09542715
申请日：2000-04-04
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3211 , H01L27/10852 , H01L28/55
摘要： A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.
摘要翻译：制造DRAM电容器的方法在形成电容器的过程中使用氮化钨。电容器的结构简单，易于执行。此外，本发明提供了一种形成氮化钨的方法，包括将氮气注入到硅化钨层中的步骤以及在氨气下执行快速热处理以在硅化钨层的表面上形成氮化钨层的步骤。制造DRAM电容器的方法包括在从掺杂多晶硅形成小于电容器的底部电极的部分之后形成硅化钨层，并在氮化钨层的表面上形成氮化钨。

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