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1. 发明申请

US20090236682A1 LAYER STACK INCLUDING A TUNGSTEN LAYER 审中-公开
标题翻译：层堆叠，包括一层金属层
公开(公告)号：US20090236682A1
公开(公告)日：2009-09-24
申请号：US12052004
申请日：2008-03-20
申请人： Hocine Boubekeur , Roman Knoefler , Hans-Peter Sperlich , Clemens Fitz , Patrick Minton
发明人： Hocine Boubekeur , Roman Knoefler , Hans-Peter Sperlich , Clemens Fitz , Patrick Minton
IPC分类号： H01L21/283 , H01L29/49
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76832 , H01L21/76834 , H01L23/53266 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described.
摘要翻译：制备层叠体的方法包括提供钨层，沉积氧化阻挡层，其在钨层顶部上免疫钨层以免氧化，以及在氧化阻挡层的顶部上沉积覆盖层。还描述了集成电路。

2. 发明授权

US06380074B1 Deposition of various base layers for selective layer growth in semiconductor production 有权
标题翻译：在半导体生产中沉积各种基层用于选择性层生长
公开(公告)号：US06380074B1
公开(公告)日：2002-04-30
申请号：US09666526
申请日：2000-09-18
申请人： Markus Kirchhoff , Hans-Peter Sperlich , Uwe Schilling , Zvonimir Gabric , Oswald Spindler , Stephan Wege , Hans Glawischnig
发明人： Markus Kirchhoff , Hans-Peter Sperlich , Uwe Schilling , Zvonimir Gabric , Oswald Spindler , Stephan Wege , Hans Glawischnig
IPC分类号： H01L214763
CPC分类号： H01L21/02129 , H01L21/02304 , H01L21/31612 , H01L21/31625 , H01L21/3185 , H01L21/76262
摘要： A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.
摘要翻译：描述了一种采用半导体电路中的无收缩空穴填充的方法，其利用被施加层的选择性生长。在该方法中，选择性生长材料层同时施加到生长促进层和生长抑制层。其中在施加选择性生长材料层之前至少在其侧面被生长抑制层覆盖的凸起部分。在施加生长抑制层之后，通过各向异性处理在凸起部分之间和之间平行于衬底的表面产生生长促进层，然后再次在凸起部分上平行于衬底的表面上去除该层。该方法使得可以以特别简单的方式产生其隆起部分上的生长抑制层在其侧面和顶部覆盖的图案，而沟槽的底部被生长促进层覆盖。

3. 发明申请

US20080038462A1 Method of forming a carbon layer on a substrate 审中-公开
标题翻译：在基材上形成碳层的方法
公开(公告)号：US20080038462A1
公开(公告)日：2008-02-14
申请号：US11501244
申请日：2006-08-09
申请人： Mirko Vogt , Hans-Peter Sperlich , Sven Frauenstein , Andre Neubauer
发明人： Mirko Vogt , Hans-Peter Sperlich , Sven Frauenstein , Andre Neubauer
IPC分类号： C23C16/00 , H05H1/24
CPC分类号： C23C16/26 , C23C16/045
摘要： The present invention relates to a method of forming a carbon layer on a substrate. A substrate with a structured surface is provided, the structured surface comprising a sidewall. A plasma is formed from an atmosphere comprising a gaseous hydrocarbon compound. The substrate is processed with the plasma, thereby depositing a carbon layer on the structured surface of the substrate. According to one aspect of the invention, the gaseous hydrocarbon compound comprises a ratio of less than 2:1 between hydrogen and carbon. According to another aspect of the invention, the atmosphere comprises a gaseous additive compound, the gaseous additive compound having an affinity for binding to hydrogen. Accordingly, the plasma comprises a reduced reactive hydrogen content, thus enabling an improved carbon deposition at the sidewall of the structured surface.
摘要翻译：本发明涉及在基材上形成碳层的方法。提供具有结构化表面的基底，所述结构化表面包括侧壁。由包含气态烃化合物的气氛形成等离子体。用等离子体处理衬底，从而在衬底的结构化表面上沉积碳层。根据本发明的一个方面，气态烃化合物在氢和碳之间的比例小于2:1。根据本发明的另一方面，气氛包括气态添加剂化合物，气态添加剂化合物具有与氢结合的亲和力。因此，等离子体包括降低的反应性氢含量，因此能够在结构化表面的侧壁处改善碳沉积。

4. 发明授权

US06293291B1 Method and apparatus for the treatment of objects, preferably wafers 有权
标题翻译：用于处理物体，优选晶片的方法和装置
公开(公告)号：US06293291B1
公开(公告)日：2001-09-25
申请号：US09289491
申请日：1999-04-09
申请人： Hans-Peter Sperlich , Volker Gajewski
发明人： Hans-Peter Sperlich , Volker Gajewski
IPC分类号： B08B1300
CPC分类号： H01L21/67276 , H01L21/67745
摘要： A method for the treatment of objects, preferably wafers, in a corresponding apparatus. The apparatus having at least two or more process chambers for receiving and treating the objects as well as a handling apparatus, for example a robot arm, for loading and unloading the process chambers. To date, all the process chambers have been loaded with the objects directly in succession. Accordingly, the actual treatment begins virtually simultaneously in all the process chambers. Furthermore, the necessary cleaning processes in the process chambers are also carried out virtually simultaneously. In order to increase the throughput of objects to be treated and to prevent or to minimize the overlapping of the cleaning processes, the invention proposes that, at the program start, at the beginning of the treatment method, the loading of the objects into the first process chamber and beginning of the treatment of the objects are effected, and that, subsequently, temporally staggered initial loading of the objects into the second process chamber and beginning of the treatment of the objects are effected. The temporally staggered initial loading of the individual process chambers can be effected by manual or computer-aided control of the apparatus. Furthermore, a corresponding apparatus is described.
摘要翻译：一种用于在相应装置中处理物体，优选晶片的方法。该装置具有用于接收和处理物体的至少两个或多个处理室，以及用于装载和卸载处理室的处理装置，例如机器人手臂。到目前为止，所有的处理室已经被连续地加载对象。因此，实际处理在所有处理室中几乎同时开始。此外，处理室中必要的清洁处理也同时进行。为了增加要处理的物体的生产量并且防止或最小化清洁过程的重叠，本发明提出，在程序开始时，在处理方法开始时，将物体加载到第一处理室和物体的开始处理，并且随后将物体初始加载到第二处理室中并开始对物体的处理。各个处理室的时间交错的初始加载可以通过手动或计算机辅助的装置控制来实现。此外，描述了相应的装置。

5. 发明授权

US06255193B1 Method for fabricating an isolation trench using an auxiliary layer 有权
标题翻译：使用辅助层制造隔离沟槽的方法
公开(公告)号：US06255193B1
公开(公告)日：2001-07-03
申请号：US09494774
申请日：2000-01-31
申请人： Hans-Peter Sperlich , Jens Zimmermann
发明人： Hans-Peter Sperlich , Jens Zimmermann
IPC分类号： H01L2170
CPC分类号： H01L27/10861 , H01L21/762 , H01L21/763
摘要： The fabrication method provides for an etched isolation trench to be lined, if appropriate firstly with a thin thermal oxide layer, and then with an oxidizable auxiliary layer. The auxiliary layer consumes oxygen during subsequent thermal processes, thereby avoiding oxidation of deeper structures, in particular of an insulation collar in a capacitor trench.
摘要翻译：制造方法提供了要被衬里的蚀刻隔离沟槽，如果适当的话首先用薄的热氧化层，然后用可氧化的辅助层。辅助层在随后的热处理期间消耗氧，从而避免更深的结构，特别是电容器沟槽中的绝缘环的氧化。

6. 发明授权

US07265023B2 Fabrication method for a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07265023B2
公开(公告)日：2007-09-04
申请号：US11099962
申请日：2005-04-06
申请人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchill Stavrev , Stephan Wege
发明人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchill Stavrev , Stephan Wege
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译：本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 进行用于在沟槽（5）中形成线层（10）的V轮廓的V等离子体蚀刻步骤; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

7. 发明申请

US20070090531A1 Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer 审中-公开
公开(公告)号：US20070090531A1
公开(公告)日：2007-04-26
申请号：US11246916
申请日：2005-10-07
申请人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
发明人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
IPC分类号： H01L23/522 , H01L21/4763
CPC分类号： H01L21/7682 , C23C16/26 , H01L21/02115 , H01L21/02126 , H01L21/02131 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

8. 发明授权

US08158485B2 Integrated circuit device having openings in a layered structure 有权
标题翻译：具有分层结构的开口的集成电路装置
公开(公告)号：US08158485B2
公开(公告)日：2012-04-17
申请号：US11744962
申请日：2007-05-07
申请人： Daniel Köhler , Manfred Engelhardt , Peter Baars , Hans-Peter Sperlich
发明人： Daniel Köhler , Manfred Engelhardt , Peter Baars , Hans-Peter Sperlich
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L21/31116 , H01L21/31144 , H01L21/76816 , H01L27/10855
摘要： An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.
摘要翻译：集成电路器件包括具有位于衬底上的第一层的衬底。第一层限定了具有沉积在第一层上并覆盖第一开口的侧壁部分的覆盖层的第一开口。第二层位于覆盖层上。第二层限定延伸穿过第二层并穿过覆盖层的第二开口以连接第一和第二开口。

9. 发明申请

US20070212849A1 Method of fabricating a groove-like structure in a semiconductor device 审中-公开
标题翻译：在半导体器件中制造凹槽状结构的方法
公开(公告)号：US20070212849A1
公开(公告)日：2007-09-13
申请号：US11373064
申请日：2006-03-10
申请人： Frank Ludwig , Kimberly Wilson , Arabinda Das , Hans-Peter Sperlich , Andreas Klipp , Kristin Schupke
发明人： Frank Ludwig , Kimberly Wilson , Arabinda Das , Hans-Peter Sperlich , Andreas Klipp , Kristin Schupke
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： The present invention relates to a method of fabricating a groove-like structure in a semiconductor device including etching a trench in a substrate, filling the trench with a spin-on-glass liquid forming a spin-on-glass liquid layer containing a solvent, baking the spin-on-glass liquid layer in order to remove the solvent and forming a baked layer, etching the baked layer to a predetermined depth using an etchant that provides a larger etch rate with regard to silicon than with regard to silicon nitride or silicon oxide, and, after etching the baked layer, annealing the remaining baked layer and forming a spin-on-glass oxide layer inside the trench.
摘要翻译：本发明涉及一种在半导体器件中制造凹槽状结构的方法，包括蚀刻衬底中的沟槽，用形成包含溶剂的旋涂玻璃液体层的旋涂玻璃液填充沟槽，烘烤旋涂玻璃液体层以除去溶剂并形成烘烤层，使用提供相对于硅的蚀刻速率比硅相对于氮化硅或硅的蚀刻剂将烘焙层蚀刻到预定深度并且在蚀刻所述烘烤层之后，对所述剩余的烘烤层进行退火并在所述沟槽内形成旋涂玻璃氧化物层。

10. 发明申请

US20050245042A1 Fabrication method for a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050245042A1
公开(公告)日：2005-11-03
申请号：US11099962
申请日：2005-04-06
申请人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
发明人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/76232
摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译：本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 执行V等离子体蚀刻步骤，用于在沟槽（5）中形成线层（10）的V轮廓; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

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