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    • 2. 发明授权
    • Fabrication method for a semiconductor structure
    • 半导体结构的制造方法
    • US07265023B2
    • 2007-09-04
    • US11099962
    • 2005-04-06
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchill StavrevStephan Wege
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchill StavrevStephan Wege
    • H01L21/76
    • H01L21/76232
    • The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
    • 本发明提供一种半导体结构的制造方法,其具有提供半导体衬底(1)的步骤。 在半导体衬底(1)上提供和图案化氮化硅层(3)作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽(5); 在所得结构上保形地沉积由氧化硅制成的衬垫层(10),留下在沟槽(5)中深入的间隙(SP); 进行用于在沟槽(5)中形成线层(10)的V轮廓的V等离子体蚀刻步骤; 其中所述衬垫层(10)被拉回到所述氮化硅层(3)的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2,在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例(V)在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。
    • 3. 发明申请
    • Fabrication method for a semiconductor structure
    • 半导体结构的制造方法
    • US20050245042A1
    • 2005-11-03
    • US11099962
    • 2005-04-06
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchil StavrevStephan Wege
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchil StavrevStephan Wege
    • H01L21/3065H01L21/762H01L21/8234H01L21/8242
    • H01L21/76232
    • The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
    • 本发明提供一种半导体结构的制造方法,其具有提供半导体衬底(1)的步骤。 在半导体衬底(1)上提供和图案化氮化硅层(3)作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽(5); 在所得结构上保形地沉积由氧化硅制成的衬垫层(10),留下在沟槽(5)中深入的间隙(SP); 执行V等离子体蚀刻步骤,用于在沟槽(5)中形成线层(10)的V轮廓; 其中所述衬垫层(10)被拉回到所述氮化硅层(3)的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2,在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例(V)在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。
    • 7. 发明授权
    • Resist stripping compositions and methods for manufacturing electrical devices
    • 抗剥离组合物和制造电气装置的方法
    • US09146471B2
    • 2015-09-29
    • US13319187
    • 2010-04-20
    • Andreas Klipp
    • Andreas Klipp
    • G03F7/42H01L21/302G03F7/20H01L21/02H01L21/311
    • G03F7/425G03F7/20H01L21/02063H01L21/31133
    • A liquid composition free from N-alkylpyrrolidones and hydroxyl amine and its derivatives, having a dynamic shear viscosity at 50° C. of from 1 to 10 mPas as measured by rotational viscometry and comprising based on the complete weight of the composition, (A) of from 40 to 99.95% by weight of a polar organic solvent exhibiting in the presence of dissolved tetramethylammonium hydroxide (B) a constant removal rate at 50° C. for a 30 nm thick polymeric barrier anti-reflective layer containing deep UV absorbing chromophoric groups, (B) of from 0.05 to
    • 一种不含N-烷基吡咯烷酮和羟胺及其衍生物的液体组合物,其在50℃下的动态剪切粘度为1至10mPas,通过旋转粘度测定测量,并包含基于组合物的完整重量,(A) 在溶解的四甲基氢氧化铵(B)的存在下显示的极性有机溶剂的40至99.95重量%,对于含有深UV吸收发色团的30nm厚的聚合物屏障抗反射层,在50℃下的恒定去除速率 ,(B)为0.05至0.5%的季铵氢氧化物,和(C)<5重量%的水; 其制备方法,用于制造电子器件的方法及其用于消除负色调和正色调光致抗蚀剂以及在制造3D堆叠集成电路和3D晶片级封装中的后蚀刻残留物的用途,通过图案化通过硅通孔和/ 或通过电镀和碰撞。
    • 9. 发明申请
    • RESIST STRIPPING COMPOSITIONS AND METHODS FOR MANUFACTURING ELECTRICAL DEVICES
    • 电阻剥离组合物和制造电气装置的方法
    • US20120058644A1
    • 2012-03-08
    • US13319187
    • 2010-04-20
    • Andreas Klipp
    • Andreas Klipp
    • H01L21/302G03F7/42
    • G03F7/425G03F7/20H01L21/02063H01L21/31133
    • A liquid composition free from N-alkylpyrrolidones and hydroxyl amine and its derivatives, having a dynamic shear viscosity at 50° C. of from 1 to 10 mPas as measured by rotational viscometry and comprising based on the complete weight of the composition, (A) of from 40 to 99.95% by weight of a polar organic solvent exhibiting in the presence of dissolved tetramethylammonium hydroxide (B) a constant removal rate at 50° C. for a 30 nm thick polymeric barrier anti-reflective layer containing deep UV absorbing chromophoric groups, (B) of from 0.05 to
    • 一种不含N-烷基吡咯烷酮和羟胺及其衍生物的液体组合物,其在50℃下的动态剪切粘度为1至10mPas,通过旋转粘度测定测量,并包含基于组合物的完整重量,(A) 在溶解的四甲基氢氧化铵(B)的存在下显示的极性有机溶剂的40至99.95重量%,对于含有深UV吸收发色团的30nm厚的聚合物屏障抗反射层,在50℃下的恒定去除速率 ,(B)为0.05至0.5%的季铵氢氧化物,和(C)<5重量%的水; 其制备方法,用于制造电子器件的方法及其用于消除负色调和正色调光致抗蚀剂以及在制造3D堆叠集成电路和3D晶片级封装中的后蚀刻残留物的用途,通过图案化通过硅通孔和/ 或通过电镀和碰撞。