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1. 发明申请

US20070264819A1 Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer 审中-公开
标题翻译：形成与半导体晶片上的布线层相关的电隔离的方法
公开(公告)号：US20070264819A1
公开(公告)日：2007-11-15
申请号：US11280802
申请日：2005-11-16
申请人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
发明人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).
摘要翻译：形成与半导体晶片的表面上的配线水平相关联的配线水平和电隔离的方法包括以下步骤：提供具有所述表面的半导体晶片，在所述表面上形成多个导电布线，布线相对于相邻的一条布线具有间隔，通过非共形等离子体增强化学气相沉积（PECVD）在布线上沉积第一层无定形碳，使得形成在下面的空气填充的空隙第一层在相邻布线之间的间隔内。或者，可以沉积OSG（有机硅玻璃）或FSG（氟掺杂硅玻璃）以在间隔内产生空气填充的空隙。根据一个实施方案，碳，OSG或FSG层用作IMD层（线对线隔离），由另外的介电材料层加入，其然后用作ILD层（水平到级隔离）。

2. 发明申请

US20070090531A1 Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer 审中-公开
公开(公告)号：US20070090531A1
公开(公告)日：2007-04-26
申请号：US11246916
申请日：2005-10-07
申请人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
发明人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
IPC分类号： H01L23/522 , H01L21/4763
CPC分类号： H01L21/7682 , C23C16/26 , H01L21/02115 , H01L21/02126 , H01L21/02131 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

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