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1. 发明授权

US06333873B1 Semiconductor memory device with an internal voltage generating circuit 失效
标题翻译：具有内部电压发生电路的半导体存储器件
公开(公告)号：US06333873B1
公开(公告)日：2001-12-25
申请号：US08942692
申请日：1997-09-29
申请人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Akira Yamazaki , Hisashi Iwamoto , Kouji Hayano
发明人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Akira Yamazaki , Hisashi Iwamoto , Kouji Hayano
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C5/146 , G11C11/005
摘要： A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.
摘要翻译：半导体存储器件接收独立于对存储器件的访问而重复产生的外部控制信号。存储器件包括用于响应于控制信号产生期望的内部电压的内部电压发生器。内部电压发生器包括响应于控制信号的电荷泵电路。内部电压可以提供诸如衬底偏置电压的负电压，或者可以是在工作电源电压上升压的正电压并且用作升压的字线驱动信号。该方案消除了用于向电荷泵电路产生重复时钟信号的振荡器，导致半导体存储器件的电流消耗降低和芯片面积减小。

2. 发明授权

US6151273A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US6151273A
公开(公告)日：2000-11-21
申请号：US362667
申请日：1999-07-29
申请人： Hisashi Iwamoto , Takeshi Kajimoto
发明人： Hisashi Iwamoto , Takeshi Kajimoto
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1072 , G11C8/18 , G11C2207/229
摘要： A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.
摘要翻译：提供了能够提高实质的传输速率的同步半导体存储器件。响应于紧跟在动作命令之后的写入命令，控制信号产生电路将无效使能信号应用于读取的前置放大器和写入缓冲器。响应于写入命令和预充电命令，控制信号产生电路产生有效使能信号，读取的前置放大器和写入缓冲器将存储在FIFO中的数据写入存储单元。由于在接收到动作命令之后的写入命令时不执行后期写入，因此可以防止数据向不想要的地址的错误写入。

3. 发明授权

US6118730A Phase comparator with improved comparison precision and synchronous semiconductor memory device employing the same 失效
标题翻译：具有改进比较精度的相位比较器和采用该比较精度的同步半导体存储器件
公开(公告)号：US6118730A
公开(公告)日：2000-09-12
申请号：US295361
申请日：1999-04-21
申请人： Takashi Kubo , Yasumitsu Murai , Hisashi Iwamoto
发明人： Takashi Kubo , Yasumitsu Murai , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/22 , H03D13/00 , H03K5/26 , H03L7/00 , H03L7/081 , H03L7/089 , G11C8/00
CPC分类号： H03L7/089 , G11C7/22 , H03D13/004 , H03K5/26 , H03L7/0814
摘要： The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.
摘要翻译：相位比较器接收接收第一输入信号的缓冲器的输出和接收第二输入信号的缓冲器的输出，并且作为相位比较的结果输出信号SLOW，FAST。相位比较器包括用于放大两个输入信号之间的相位差的波形处理电路和用于通过波形处理电路放大的相位差进行相位比较的比较电路，并输出信号SLOW，FAST。由于波形处理电路的功能，可以显着提高相位比较器的性能，而不必大幅提高比较电路的性能。

4. 发明授权

US5940344A Synchronous semiconductor memory device including internal clock signal generation circuit that generates an internal clock signal synchronizing in phase with external clock signal at high precision 失效
标题翻译：同步半导体存储器件包括内部时钟信号产生电路，其产生与外部时钟信号同步高精度的内部时钟信号
公开(公告)号：US5940344A
公开(公告)日：1999-08-17
申请号：US53058
申请日：1998-04-01
申请人： Yasumitsu Murai , Wataru Sakamoto , Hisashi Iwamoto
发明人： Yasumitsu Murai , Wataru Sakamoto , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22
摘要： In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.
摘要翻译：在内部时钟信号发生电路中，用于检测外部时钟信号和内部时钟信号之间的相位差的相位比较器包括相对于信号线的晶体管和电容器，通过该信号线发送对应于外部时钟信号的时钟信号以及相对于信号线的晶体管和电容器，通过该晶体管和电容器发送与内部时钟信号对应的时钟信号。具有两个信号线的信号的滞后相位的信号的上升定时变得更加平缓。结果，相位差增大，相位比较器可以高精度地比较相位。

5. 发明授权

US5844859A Synchronous semiconductor memory device reliably fetching external signal in synchronization with clock signal periodically supplied from the exterior 失效
标题翻译：同步半导体存储器件与从外部周期性提供的时钟信号同步地可靠地取得外部信号
公开(公告)号：US5844859A
公开(公告)日：1998-12-01
申请号：US923689
申请日：1997-09-04
申请人： Hisashi Iwamoto , Yasuhiro Konishi
发明人： Hisashi Iwamoto , Yasuhiro Konishi
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.
摘要翻译：当操作频率增加并且CAS延迟设置得更长时，响应于CAS延迟的改变，数据写入结束时间被延迟特定时间。具体时间大于对应于CAS延迟的周期。具体时间可以是写入第二位数据所需的最短时间。也可以通过将外部时钟信号的一个时钟周期延迟存储器本身内部的写入定时（激活和去激活）来扩大写入裕度。因此，即使操作频率增加，也可以在SDRAM中确保第二位数据的写周期。

6. 发明授权

US5404338A Synchronous type semiconductor memory device operating in synchronization with an external clock signal 失效
标题翻译：与外部时钟信号同步工作的同步型半导体存储器件
公开(公告)号：US5404338A
公开(公告)日：1995-04-04
申请号：US189247
申请日：1994-01-31
申请人： Yasumitsu Murai , Hisashi Iwamoto , Yasuhiro Konishi , Naoya Watanabe , Seiji Sawada
发明人： Yasumitsu Murai , Hisashi Iwamoto , Yasuhiro Konishi , Naoya Watanabe , Seiji Sawada
IPC分类号： G11C11/407 , F02B75/02 , G11C7/10 , G11C11/401 , G11C11/409 , G11C13/00
CPC分类号： G11C7/222 , G11C7/1072 , F02B2075/027
摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.
摘要翻译：在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。提供了两个小型存储器阵列的本地I / O线对（LIO）。跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。从而，可以同时读取多个比特，而不增加互连占用的面积。使用读出放大器激活信号进行连接开关的控制。数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。

7. 发明授权

US5384745A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5384745A
公开(公告)日：1995-01-24
申请号：US46333
申请日：1993-04-14
申请人： Yasuhiro Konishi , Takayuki Miyamoto , Takeshi Kajimoto , Hisashi Iwamoto
发明人： Yasuhiro Konishi , Takayuki Miyamoto , Takeshi Kajimoto , Hisashi Iwamoto
IPC分类号： G11C7/10 , G11C8/12 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
摘要翻译：存储器阵列被分成可以相互独立操作的存储体。为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。全局IO线连接到前置放大器组并写入缓冲组。通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止对所需位的写入，如果数据写入应当是数据写入时，可以将数据集中写入所选存储单元在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。

8. 发明申请

US20130039134A1 SEMICONDUCTOR DEVICE INCLUDING MEMORY CAPABLE OF REDUCING POWER CONSUMPTION 有权
标题翻译：半导体器件，包括可减少功耗的存储器
公开(公告)号：US20130039134A1
公开(公告)日：2013-02-14
申请号：US13566779
申请日：2012-08-03
申请人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
发明人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
IPC分类号： G11C7/22
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1096 , G11C7/222
摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.
摘要翻译：半导体器件包括多个存储器阵列和多个存储器阵列控制电路。多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路读/写控制电路。

9. 发明授权

US06763079B1 Semiconductor device allowing easy confirmation of operation of built in clock generation circuit 失效
标题翻译：半导体器件允许容易地确认内置时钟发生电路的操作
公开(公告)号：US06763079B1
公开(公告)日：2004-07-13
申请号：US09252910
申请日：1999-02-19
申请人： Hisashi Iwamoto
发明人： Hisashi Iwamoto
IPC分类号： H04L708
CPC分类号： G11C29/12015 , G01R31/31725 , G01R31/31727 , G11C29/02 , G11C29/50012 , H03K5/133 , H03K2005/00071 , H03K2005/00241 , H03L7/0814 , H03L7/089
摘要： A shift register which outputs a delay control signal for a delay line is made controllable at a test mode by a TEST MODE address buffer receiving an external address as a control signal and a phase comparator. Thus whether the delay of the delay line is correctly controlled or not can be confirmed through observation of an internal clock signal int. CLK output from an output buffer at the test and an external clock signal ext. CLK.
摘要翻译：输出用于延迟线的延迟控制信号的移位寄存器通过接收作为控制信号的外部地址的TEST MODE地址缓冲器和相位比较器在测试模式下被控制。因此，可以通过观察内部时钟信号int来确认延迟线的延迟是否被正确控制。来自测试时的输出缓冲器的CLK输出和外部时钟信号分频。 CLK。

10. 发明授权

US06741507B2 Semiconductor device outputting data at a timing with reduced jitter 失效
标题翻译：半导体器件在抖动减小的定时输出数据
公开(公告)号：US06741507B2
公开(公告)日：2004-05-25
申请号：US10224343
申请日：2002-08-21
申请人： Hisashi Iwamoto
发明人： Hisashi Iwamoto
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/222
摘要： In a DLL circuit between a phase comparator and a digital filter there is provided a signal switching portion preventing control signals UP and DOWN from being transmitted after a clock enable signal extCKE is activated and before a predetermined period of time elapses. Thus after a semiconductor device returns from a power down mode and before a predetermined period of time elapses it continues to stop updating an amount of delay of a delay line. Thus before an internal power supply potential stabilizes the delay line does not have a varying amount of delay and as a result the semiconductor device can output data at a timing free of significant fluctuation.
摘要翻译：在相位比较器和数字滤波器之间的DLL电路中，提供了一个信号切换部分，该信号切换部分防止在时钟使能信号extCKE被激活之后并在经过预定时间段之前传输控制信号UP和DOWN。因此，在半导体器件从断电模式返回并且在经过预定时间段之前，它继续停止更新延迟线的延迟量。因此，在内部电源电位稳定之前，延迟线不具有变化的延迟量，因此半导体器件可以在没有显着波动的时刻输出数据。

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