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1. 发明授权

US5940344A Synchronous semiconductor memory device including internal clock signal generation circuit that generates an internal clock signal synchronizing in phase with external clock signal at high precision 失效
标题翻译：同步半导体存储器件包括内部时钟信号产生电路，其产生与外部时钟信号同步高精度的内部时钟信号
公开(公告)号：US5940344A
公开(公告)日：1999-08-17
申请号：US53058
申请日：1998-04-01
申请人： Yasumitsu Murai , Wataru Sakamoto , Hisashi Iwamoto
发明人： Yasumitsu Murai , Wataru Sakamoto , Hisashi Iwamoto
IPC分类号： G11C11/407 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22
摘要： In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.
摘要翻译：在内部时钟信号发生电路中，用于检测外部时钟信号和内部时钟信号之间的相位差的相位比较器包括相对于信号线的晶体管和电容器，通过该信号线发送对应于外部时钟信号的时钟信号以及相对于信号线的晶体管和电容器，通过该晶体管和电容器发送与内部时钟信号对应的时钟信号。具有两个信号线的信号的滞后相位的信号的上升定时变得更加平缓。结果，相位差增大，相位比较器可以高精度地比较相位。

2. 发明授权

US06184738B2 Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential 失效
标题翻译：输入缓冲器，用于根据外部信号与参考电位的比较为半导体器件提供内部信号
公开(公告)号：US06184738B2
公开(公告)日：2001-02-06
申请号：US09019199
申请日：1998-02-05
申请人： Hisashi Iwamoto , Aiko Nishino , Wataru Sakamoto
发明人： Hisashi Iwamoto , Aiko Nishino , Wataru Sakamoto
IPC分类号： H03L500
CPC分类号： H03K19/018528
摘要： An input buffer of a semiconductor device is provided. A first voltage shift circuit converts an input signal formed of a low amplitude logic signal overlapping 1.65V or 2.9V to a first signal formed of a complimentary signal formed of the low amplitude logic signal overlapping 2.9V or 1.65V. A second voltage shift circuit converts a reference potential of 1.65V or 2.9V to a second signal of 2.9V or 1.65V. A differential amplifier compares the reference potential with the input signal when the reference potential is 1.65V, and compares the first signal and the second signal when the reference potential is 2.9V. The input buffer thus operates normally whichever of 1.65V and 2.9V is the reference potential.
摘要翻译：提供半导体器件的输入缓冲器。第一电压移位电路将由1.65V或2.9V重叠的低幅度逻辑信号形成的输入信号转换成由与低幅度逻辑信号形成的互补信号形成的第一信号重叠2.9 V或1.65V。第二电压移位电路将1.65V或2.9V的参考电位转换为2.9V或1.65V的第二信号。当参考电位为1.65V时，差分放大器将参考电位与输入信号进行比较，当参考电位为2.9V时，比较第一信号和第二信号。因此，输入缓冲器通常正常为1.65V和2.9V为参考电位。

3. 发明授权

US06292040B1 Internal clock signal generating circuit having function of generating internal clock signals which are multiplication of an external clock signal 失效
标题翻译：内部时钟信号发生电路具有产生与外部时钟信号相乘的内部时钟信号的功能
公开(公告)号：US06292040B1
公开(公告)日：2001-09-18
申请号：US09047375
申请日：1998-03-25
申请人： Hisashi Iwamoto , Wataru Sakamoto , Naoya Watanabe
发明人： Hisashi Iwamoto , Wataru Sakamoto , Naoya Watanabe
IPC分类号： H03L706
CPC分类号： H03L7/07 , H03K23/544 , H03L7/0814 , H03L7/089 , Y10S331/02
摘要： An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency divider, a phase comparator and a shift register. The selector alternately selects an external clock signal and an internal clock signal output from the delay line and outputs the selected signal to the delay line. The delay line receiving the signal delays the external clock signal, and delays the internal clock signal output from itself. The 2-frequency divider divides frequency of the internal clock signal by 2. Phase comparator compares phases of the external clock signal and the output signal from the 2-frequency divider. Delay time of the delay line is adjusted by the phase comparator and the shift register so that the phase difference is made 0.
摘要翻译：内部时钟信号发生电路包括选择器，延迟线，2分频器，相位比较器和移位寄存器。选择器交替地选择从延迟线输出的外部时钟信号和内部时钟信号，并将选择的信号输出到延迟线。接收信号的延迟线延迟外部时钟信号，并延迟其自身输出的内部时钟信号。 2分频器将内部时钟信号的频率除以2.相位比较器比较外部时钟信号和2分频器的输出信号的相位。延迟线的延迟时间由相位比较器和移位寄存器调整，使得相位差为0。

4. 发明授权

US5940328A Synchronous semiconductor device with memory chips in a module for controlling output of strobe signal for trigger in reading data 失效
标题翻译：具有存储器芯片的同步半导体器件，用于控制用于在读取数据中触发的选通信号的输出
公开(公告)号：US5940328A
公开(公告)日：1999-08-17
申请号：US917211
申请日：1997-08-25
申请人： Hisashi Iwamoto , Wataru Sakamoto
发明人： Hisashi Iwamoto , Wataru Sakamoto
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C11/407 , G11C16/04
CPC分类号： G11C7/1072 , G11C7/22
摘要： One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1)) inputted to the adjacent first memory chip (MC(i-1)) as a data mask control signal (DQMCi), and stops outputting the strobe signal (QS) when both the data mask signal (DQMi) for the second memory chip (MCi) and the data mask control signal (DQMCi) are activated. Each memory chip (MCi) receives the data mask signal (DQMi) and stops outputting data. In a synchronous DRAM using a strobe signal as a trigger, this configuration allows reduction in the number of strobe signals.
摘要翻译：在每个模块中从一组两个相邻的存储器芯片（MC（i-1），MCi）输出一个选通信号（QS）。在每组中，第二存储器芯片（MCi）接收输入到相邻的第一存储器芯片（MC（i-1））的数据掩码信号（DQM（i-1））作为数据掩码控制信号（DQMCi），以及当第二存储器芯片（MCi）的数据掩码信号（DQMi）和数据掩码控制信号（DQMCi）都被激活时，停止输出选通信号（QS）。每个存储器芯片（MCi）接收数据屏蔽信号（DQMi）并停止输出数据。在使用选通信号作为触发的同步DRAM中，该配置允许减少选通信号的数量。

5. 发明授权

US08837223B2 Nonvolatile semiconductor memory device and method for manufacuring the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08837223B2
公开(公告)日：2014-09-16
申请号：US13600991
申请日：2012-08-31
申请人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
发明人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , H01L21/28 , H01L29/788 , G11C16/10
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L21/28273 , H01L27/11524 , H01L27/11531 , H01L29/788
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.
摘要翻译：根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层，栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。

6. 发明申请

US20130235666A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130235666A1
公开(公告)日：2013-09-12
申请号：US13600991
申请日：2012-08-31
申请人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
发明人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
IPC分类号： G11C16/04 , H01L29/788 , H01L21/28
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L21/28273 , H01L27/11524 , H01L27/11531 , H01L29/788
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.
摘要翻译：根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层，栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。

7. 发明授权

US08212303B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08212303B2
公开(公告)日：2012-07-03
申请号：US12821689
申请日：2010-06-23
申请人： Wataru Sakamoto
发明人： Wataru Sakamoto
IPC分类号： H01L29/94
CPC分类号： H01L29/42324 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11529 , H01L27/11548 , H01L27/11575 , H01L29/4234
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions, first active regions provided in the first region and each having a first width, second active regions provided in the second region and each having a second width greater than the first width, third active regions provided in the third region and each having a third with greater than the first width. An upper surface of an element isolation layer in the second region is higher than that of an element isolation layer in the first region.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：半导体衬底，包括其中布置有存储单元晶体管的第一区域;第二区域，其中布置提取与存储单元晶体管电连接的字线的电极;以及其中配置有外围晶体管的第三区域，所述半导体衬底包括分隔相邻有源区的元件隔离层，设置在所述第一区域中的每一个具有第一宽度的第一有源区，并且每个具有第一宽度，所述第二有源区设置在所述第二区中，具有大于第一宽度的第二宽度，设置在第三区域中的每一个具有大于第一宽度的第三有效区域。第二区域中的元件隔离层的上表面高于第一区域中的元件隔离层的上表面。

8. 发明申请

US20100194343A1 BATTERY STATE MONITORING CIRCUIT AND BATTERY DEVICE 有权
标题翻译：电池状态监测电路和电池装置
公开(公告)号：US20100194343A1
公开(公告)日：2010-08-05
申请号：US12699593
申请日：2010-02-03
申请人： Kazuaki Sano , Wataru Sakamoto , Toshiyuki Koike , Muneharu Kawana
发明人： Kazuaki Sano , Wataru Sakamoto , Toshiyuki Koike , Muneharu Kawana
IPC分类号： H02J7/00
CPC分类号： H02J7/0016 , H02J7/0021 , H02J7/0026
摘要： Provided are a battery state monitoring circuit and a battery device which are capable of inhibiting discharge without enabling an overdischarge cell balance function when an overcurrent detection circuit detects a discharge overcurrent, without the need for an additional terminal of the battery state monitoring circuit. A detection signal of the overcurrent detection circuit is input to each of a communication terminal for overdischarge signal and a communication terminal for overcharge signal included in the battery state monitoring circuit provided on a side of the overcurrent detection circuit. An overdischarge cell balance circuit outputs a cell balance signal when an overdischarge detection signal indicates an overdischarge non-detected state, an overdischarge signal indicates an overdischarge detected state, and an overcharge signal indicates an overcharge non-detected state.
摘要翻译：提供一种电池状态监视电路和电池装置，其能够在过电流检测电路检测到放电过电流时能够抑制放电，而不需要过放电电池平衡功能，而不需要电池状态监视电路的附加端子。过电流检测电路的检测信号输入到过放电信号的通信端子和设置在过电流检测电路一侧的电池状态监视电路中的过充电信号的通信端子。当过放电检测信号表示过放电未检测状态，过放电信号表示过放电检测状态，过充电单元平衡电路输出单元平衡信号，过充电信号表示过充电未检测状态。

9. 发明申请

US20090053885A1 MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE USING INSULATING FILM AS CHARGE STORAGE LAYER 有权
标题翻译：使用绝缘膜作为充电储存层的半导体存储器件的制造方法
公开(公告)号：US20090053885A1
公开(公告)日：2009-02-26
申请号：US12194050
申请日：2008-08-19
申请人： Wataru Sakamoto , Mitsuhiro Noguchi
发明人： Wataru Sakamoto , Mitsuhiro Noguchi
IPC分类号： H01L21/3205
CPC分类号： H01L21/31133 , H01L21/28282 , H01L21/823425 , H01L21/823468 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor memory device includes forming a first gate electrode having a charge storage layer, a block layer, and a control gate electrode on a first region of a semiconductor substrate, forming a second gate electrode on a second region of the semiconductor substrate, forming a protective insulating film on a side surface of the block layer, exposing the first region while covering the second region on the semiconductor substrate with a photoresist, using the photoresist, the first gate electrode, and the protective insulating film as masks to implant an impurity into the first region of the semiconductor substrate, and removing the photoresist by wet etching which uses a mixed solution containing H2SO4 and H2O2. The protective insulating film having an etching selective ratio of 1:100 or above with respect to the photoresist under wet etching conditions using the mixed solution.
摘要翻译：半导体存储器件的制造方法包括在半导体衬底的第一区域上形成具有电荷存储层的第一栅电极，阻挡层和控制栅电极，在半导体衬底的第二区域上形成第二栅电极衬底，在阻挡层的侧表面上形成保护绝缘膜，使用光致抗蚀剂，第一栅极电极和保护绝缘膜作为掩模，用光致抗蚀剂暴露第一区域同时覆盖半导体衬底上的第二区域，将杂质注入半导体衬底的第一区域，并通过使用含有H 2 SO 4和H 2 O 2的混合溶液的湿法蚀刻去除光致抗蚀剂。该保护绝缘膜在湿蚀刻条件下使用混合溶液相对于光致抗蚀剂的蚀刻选择比为1:100或更高。

10. 发明授权

US6120750A Method of producing lead-containing complex oxides 有权
标题翻译：生产含铅复合氧化物的方法
公开(公告)号：US6120750A
公开(公告)日：2000-09-19
申请号：US273275
申请日：1999-03-22
申请人： Shinichi Hirano , Yusuke Hirabayashi , Toshinobu Yogo , Wataru Sakamoto
发明人： Shinichi Hirano , Yusuke Hirabayashi , Toshinobu Yogo , Wataru Sakamoto
IPC分类号： C01G25/00 , C01G23/02 , C01G21/02 , C01G25/02
CPC分类号： C01G25/006 , C01P2002/34
摘要： A lead-containing complex oxide containing substantially no alkali metal is produced under hydrothermal conditions in the absence of alkali metals using a Pb source which serves also as a mineralizer for precipitating the lead-containing complex oxide. Preferred Pb source acting as the mineralizer is lead oxide.
摘要翻译：在不存在碱金属的水热条件下，使用也用作沉淀含铅复合氧化物的矿化剂的Pb源产生基本上不含碱金属的含铅复合氧化物。作为矿化剂的优选Pb源是氧化铅。

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