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1. 发明授权

US06333873B1 Semiconductor memory device with an internal voltage generating circuit 失效
标题翻译：具有内部电压发生电路的半导体存储器件
公开(公告)号：US06333873B1
公开(公告)日：2001-12-25
申请号：US08942692
申请日：1997-09-29
申请人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Akira Yamazaki , Hisashi Iwamoto , Kouji Hayano
发明人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Akira Yamazaki , Hisashi Iwamoto , Kouji Hayano
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C5/146 , G11C11/005
摘要： A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.
摘要翻译：半导体存储器件接收独立于对存储器件的访问而重复产生的外部控制信号。存储器件包括用于响应于控制信号产生期望的内部电压的内部电压发生器。内部电压发生器包括响应于控制信号的电荷泵电路。内部电压可以提供诸如衬底偏置电压的负电压，或者可以是在工作电源电压上升压的正电压并且用作升压的字线驱动信号。该方案消除了用于向电荷泵电路产生重复时钟信号的振荡器，导致半导体存储器件的电流消耗降低和芯片面积减小。

2. 发明授权

US5650968A Semiconductor memory device 失效
公开(公告)号：US5650968A
公开(公告)日：1997-07-22
申请号：US655322
申请日：1996-05-21
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

3. 发明授权

US5623454A Semiconductor memory device 失效
公开(公告)号：US5623454A
公开(公告)日：1997-04-22
申请号：US599265
申请日：1996-02-09
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

4. 发明授权

US06170036A Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM 失效
标题翻译：用于在DRAM和SRAM之间传送数据的半导体存储器件和数据传输电路
公开(公告)号：US06170036A
公开(公告)日：2001-01-02
申请号：US08780066
申请日：1996-12-23
申请人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
发明人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
IPC分类号： G06F1300
CPC分类号： G11C7/1006 , G06F12/0893 , G11C7/103 , G11C7/1045 , G11C11/005 , G11C2207/2254
摘要： A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.
摘要翻译：半导体存储器件被配置为包括静态随机存取存储器（SRAM）阵列和动态随机存取存储器（DRAM）阵列。存储器件包括内部数据线，其能够在SRAM和DRAM阵列之间传输数据块。数据传输电路与内部数据线分开提供，并且包括用于锁存要传送的数据的锁存电路。数据传输电路响应传输指定信号。

5. 发明授权

US6026029A Semiconductor memory device 失效
公开(公告)号：US6026029A
公开(公告)日：2000-02-15
申请号：US865310
申请日：1997-05-29
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

6. 发明授权

US5848004A Semiconductor memory device 失效
公开(公告)号：US5848004A
公开(公告)日：1998-12-08
申请号：US625578
申请日：1996-03-28
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

7. 发明授权

US5603009A Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM 失效
标题翻译：半导体存储器件包括用于在DRAM和SRAM之间传送数据的数据传输电路
公开(公告)号：US5603009A
公开(公告)日：1997-02-11
申请号：US356046
申请日：1994-12-14
申请人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
发明人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G06F13/00 , G11C11/34
CPC分类号： G11C7/1006 , G06F12/0893 , G11C11/005 , G11C7/103 , G11C7/1045 , G11C2207/2254
摘要： A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.
摘要翻译：包含高速缓存的半导体存储器件包括作为高速缓冲存储器的静态随机存取存储器（SRAM）和作为主存储器的动态随机存取存储器（DRAM）。通过双向数据传输门电路和内部数据线，可以在DRAM和SRAM之间进行数据块的集中传输。在DRAM中提供DRAM行解码器和DRAM列解码器。在SRAM中提供SRAM行解码器和SRAM列解码器。 SRAM和DRAM的地址可以独立应用。数据传输门包括一个锁存电路，用于锁存来自用作高速存储器的SRAM的数据，放大器电路和用于放大来自DRAM的数据的门电路，其用作大容量存储器，并用于发送放大数据到SRAM，以及门电路，响应于用于将写入数据发送到DRAM的相应存储器单元的DRAM写使能信号。在SRAM的数据被锁存电路锁存之后，写入数据从门电路传输到DRAM，写数据通过放大电路和门电路传输到SRAM。

8. 发明授权

US06434661B1 Synchronous semiconductor memory including register for storing data input and output mode information 失效
标题翻译：同步半导体存储器包括用于存储数据输入和输出模式信息的寄存器
公开(公告)号：US06434661B1
公开(公告)日：2002-08-13
申请号：US09640518
申请日：2000-08-17
申请人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
发明人： Yasuhiro Konishi , Katsumi Dosaka , Kouji Hayano , Masaki Kumanoya , Akira Yamazaki , Hisashi Iwamoto
IPC分类号： G06F1300
CPC分类号： G11C7/1006 , G06F12/0893 , G11C7/103 , G11C7/1045 , G11C11/005 , G11C2207/2254
摘要： A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.
摘要翻译：半导体存储器件具有用作高速缓冲存储器的静态随机存取存储器（SRAM）和用作主存储器的动态随机存取存储器（DRAM）。双向数据传输电路被布置用于在SRAM和DRAM之间传送数据块。提供了一个命令寄存器来保存命令数据以设置诸如存储器件的数据输出模式的操作模式。数据输出模式可以包括根据存储器件的数据输入端子处的数据组合选择的透明模式，锁存模式和注册模式。用于提供选择的数据输出模式的输出电路包括用于响应于时钟信号在读取数据总线上锁存数据的输出锁存电路，以及用于将数据从输出锁存器输出到数据输出端的输出缓冲器。当命令数据具有第一值时，锁存电路以时钟信号的第一时钟周期提供数据，并且当命令数据具有第一时钟周期时，提供比第一时钟周期晚的时钟信号的第二时钟周期的数据第二个值。

9. 发明授权

US06356484B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06356484B2
公开(公告)日：2002-03-12
申请号：US09480006
申请日：2000-01-10
申请人： Katsumi Dosaka , Masaki Kumanoya , Yasuhiro Konishi , Katsumitsu Himukashi , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Ishizuka , Tsukasa Saika
发明人： Katsumi Dosaka , Masaki Kumanoya , Yasuhiro Konishi , Katsumitsu Himukashi , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Ishizuka , Tsukasa Saika
IPC分类号： G11C1100
CPC分类号： G11C8/00 , G06F12/0893 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02D10/13
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
摘要翻译：半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。数据写入路径和数据读取路径分别设置在DRAM阵列中。通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高高速运行即使在缓存未命中。

10. 发明授权

US5652723A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5652723A
公开(公告)日：1997-07-29
申请号：US869917
申请日：1992-04-15
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
摘要翻译：半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。数据写入路径和数据读取路径分别设置在DRAM阵列中。通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高高速运行即使在缓存未命中。

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