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1. 发明授权

US4563807A Method for making semiconductor device utilizing molecular beam epitaxy to form the emitter layers 失效
标题翻译：制造半导体器件利用分子束外延形成发射极层的方法
公开(公告)号：US4563807A
公开(公告)日：1986-01-14
申请号：US596592
申请日：1984-04-04
申请人： Hiroyuki Sakai , Toyoki Takemoto , Kenji Kawakita , Tsutomu Fujita , Atsuko Akiyama
发明人： Hiroyuki Sakai , Toyoki Takemoto , Kenji Kawakita , Tsutomu Fujita , Atsuko Akiyama
IPC分类号： H01L21/20 , H01L21/203 , H01L21/285 , H01L21/331 , H01L29/73 , H01L29/732 , H01L21/225
CPC分类号： H01L29/7325 , H01L21/02532 , H01L21/02576 , H01L21/02631 , H01L21/28525 , Y10S148/123 , Y10S148/124 , Y10S148/169
摘要： Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.
摘要翻译：诸如双极晶体管的半导体器件通过分子束外延制造，其中发射极层（27）和多晶硅的覆盖接触区域（28）在硅衬底（23 + 26）上连续生长而不破坏高真空，因此消除多晶硅层（28）下的自然氧化膜的不利界面和不利的供体 - 受体补偿，同时实现良好控制的hFE并实现浅发射极结。

2. 发明授权

US4563227A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4563227A
公开(公告)日：1986-01-07
申请号：US660255
申请日：1984-10-12
申请人： Hiroyuki Sakai , Kenji Kawakita , Tsutomu Fujita , Toyoki Takemoto
发明人： Hiroyuki Sakai , Kenji Kawakita , Tsutomu Fujita , Toyoki Takemoto
IPC分类号： H01L21/762 , H01L21/38 , H01L21/467
CPC分类号： H01L21/76232 , H01L21/762
摘要： The invention provides a method for manufacturing a semiconductor device, wherein a semiconductor substrate is vertically etched to form a groove, antioxidant insulating films are formed on the side walls of the groove, and local oxidation is performed. Lateral extrusion of an oxide film which is a so-called bird's beak and a projection of the oxide film which is a so-called bird's head are substantially eliminated. As a result, the active region of the transistor, that is, the element formation region may not be narrowed, providing high packing density and high precision. Furthermore, the surface of the semiconductor substrate is flattened to prevent short-circuiting and disconnections of wiring layers. Stable manufacturing process provides a high yield of the semiconductor device. Electrical characteristics of the semiconductor device are greatly improved.
摘要翻译：本发明提供一种制造半导体器件的方法，其中半导体衬底被垂直蚀刻以形成沟槽，在沟槽的侧壁上形成抗氧化绝缘膜，并进行局部氧化。基本上消除了所谓的鸟喙的氧化膜的侧向挤出和所谓的鸟头的氧化膜的突起。结果，晶体管的有源区，即元件形成区域可能不会变窄，提供高的堆积密度和高精度。此外，半导体衬底的表面被平坦化以防止布线层的短路和断开。稳定的制造工艺提供了高产量的半导体器件。半导体器件的电气特性大大提高。

3. 发明授权

US4814287A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US4814287A
公开(公告)日：1989-03-21
申请号：US82212
申请日：1987-08-06
申请人： Toyoki Takemoto , Kenji Kawakita , Hiroyuki Sakai
发明人： Toyoki Takemoto , Kenji Kawakita , Hiroyuki Sakai
IPC分类号： H01L27/00 , H01L21/74 , H01L21/762 , H01L21/763 , H01L21/8222 , H01L21/8236 , H01L27/06 , H01L27/088 , H01L21/76 , H01L21/95
CPC分类号： H01L21/743 , H01L21/76245 , H01L21/76264 , H01L21/763 , H01L21/7627 , H01L21/76281
摘要： A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.
摘要翻译：一种制造双极型MOS型半导体集成电路器件的方法或者具有高集成度和高性能的两种类型的集成方法，其中电路包括第一器件区域，其中第一器件区域的侧表面和整个区域有源区的下部由氧化硅制成，其第二器件区的有源区的侧表面和下部的一部分由氧化硅制成。根据本发明，底部开放的晶体管和其底部未打开的晶体管可以自由地设置在基板上，从而将晶体管分成从基板提供电压的晶体管和晶体管不能从基板供给电压，从而可以减少传统上需要的布线。此外，在完全分离的这种晶体管中，完全防止与圆周的寄生效应，从而可以提供优异的特性。

4. 发明授权

US4615746A Method of forming isolated island regions in a semiconductor substrate by selective etching and oxidation and devices formed therefrom 失效
标题翻译：通过选择性蚀刻和氧化在半导体衬底中形成隔离岛区域的方法和由其形成的器件
公开(公告)号：US4615746A
公开(公告)日：1986-10-07
申请号：US652096
申请日：1984-09-19
申请人： Kenji Kawakita , Hiroyuki Sakai , Toyoki Takemoto
发明人： Kenji Kawakita , Hiroyuki Sakai , Toyoki Takemoto
IPC分类号： H01L21/22 , H01L21/762 , H01L21/225 , H01L21/302
CPC分类号： H01L21/22 , H01L21/76264 , H01L21/76281
摘要： A method of fabricating a semiconductor device comprises the steps of forming oxidation-resistive films on the surface and sides of a protrusion formed on a semiconductor substrate, forming grooves at the bottom of the sides of the protrusion, forming highly doped impurity diffusion regions in the groove surfaces, and subjecting the grooves to selective oxidation to form an oxide film under the bottom of the protrusion while a highly doped impurity diffusion region is formed, and forming a device in the protrusion.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成在半导体衬底上的突起的表面和侧面上形成耐氧化膜，在突起的侧面的底部形成凹槽，在其中形成高掺杂杂质扩散区凹槽表面，并且使凹槽经受选择性氧化，以在突起的底部形成氧化膜，同时形成高度掺杂的杂质扩散区，并在突起中形成器件。

5. 发明授权

US4459496A Semiconductor integrated circuit having stacked integrated injection logic circuits 失效
标题翻译：具有层叠集成注入逻辑电路的半导体集成电路
公开(公告)号：US4459496A
公开(公告)日：1984-07-10
申请号：US251966
申请日：1981-04-03
申请人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
发明人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
IPC分类号： H03K19/091 , H03K19/092
CPC分类号： H03K19/091
摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.
摘要翻译：在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。

6. 发明授权

US4484211A Oxide walled emitter 失效
标题翻译：氧化物壁发射体
公开(公告)号：US4484211A
公开(公告)日：1984-11-20
申请号：US542555
申请日：1983-10-17
申请人： Toyoki Takemoto , Tsutomu Fujita , Hiroyuki Sakai , Haruyasu Yamada
发明人： Toyoki Takemoto , Tsutomu Fujita , Hiroyuki Sakai , Haruyasu Yamada
IPC分类号： H01L29/06 , H01L29/732 , H01L27/04 , H01L29/04 , H01L29/72
CPC分类号： H01L29/7325 , H01L29/0649
摘要： A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.
摘要翻译：一种半导体集成电路器件，其中氧化物隔离双极晶体管的发射极的侧表面被绝缘化合物或区域包围，使得发射极和基极之间的电容降低，并且通过自对准形成基极，活性碱在外部碱基和发光体之间的影响可以忽略不计。因此，基极电阻和寄生电容降低。

7. 发明授权

US4685198A Method of manufacturing isolated semiconductor devices 失效
标题翻译：制造隔离半导体器件的方法
公开(公告)号：US4685198A
公开(公告)日：1987-08-11
申请号：US758962
申请日：1985-07-25
申请人： Kenji Kawakita , Noboru Nomura , Toyoki Takemoto
发明人： Kenji Kawakita , Noboru Nomura , Toyoki Takemoto
IPC分类号： H01L21/762 , H01L21/763 , H01L29/06
CPC分类号： H01L21/76264 , H01L21/762 , H01L21/763 , H01L21/76281 , H01L21/76283 , Y10S148/05 , Y10S148/115 , Y10S438/973
摘要： Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.
摘要翻译：公开了通过采用选择氧化技术（LOCOS技术）将晶体管完全隔离的方法。更具体地，在{100}硅衬底的表面中形成垂直开口，并且由该表面和这些开口的一部分侧壁形成抗氧化膜。相继地，通过用具有取向各向异性的蚀刻剂进行蚀刻，在开口的侧壁中以高精度形成凹痕。通过使用抗氧化膜作为掩模进行氧化，从开口侧壁中的凹陷生长的氧化膜与从相邻凹坑生长的另一氧化膜连接。因此，在与衬底电隔离的硅的有源区中形成的晶体管的寄生电容小，并且可以形成为小尺寸，使得其具有适合于VLSI的特征，即高速度，低功耗，和可加工性的高密度集成。

8. 发明授权

US5066602A Method of making semiconductor IC including polar transistors 失效
标题翻译：制造包含极性晶体管的半导体IC的方法
公开(公告)号：US5066602A
公开(公告)日：1991-11-19
申请号：US295380
申请日：1989-01-10
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092
CPC分类号： H01L27/0244 , H01L21/74 , H01L21/761 , H01L21/82285 , H01L27/0623 , H01L27/0826 , H01L27/0922 , Y10S148/009 , Y10S148/151
摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

9. 发明授权

US5661066A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5661066A
公开(公告)日：1997-08-26
申请号：US965967
申请日：1991-04-02
申请人： Toyoki Takemoto , Haruyasu Yamada , Tsutomu Fujita , Tadao Komeda
发明人： Toyoki Takemoto , Haruyasu Yamada , Tsutomu Fujita , Tadao Komeda
IPC分类号： H01L21/8222 , H01L27/02 , H01L27/06 , H01L29/8605 , H01L29/93 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/0233 , H01L21/8222 , H01L27/0244 , H01L27/0647 , H01L29/8605 , H01L29/93
摘要： In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.
摘要翻译：在包括IIL和高频npn双极晶体管的集成电路中，其具有用于其反相npn输出晶体管的深p型基极区45，电路元件如电阻器部分R，电容器部分C，二极管部分D 并且隔离交叉连接部分Cr设置有与IIL中的p型区域45同时形成的深P型区域54,54'，65'，71和82，从而可靠性的电路元件及其特性得到改善，从而进一步提高了制造成品率。

10. 发明授权

US4826780A Method of making bipolar transistors 失效
标题翻译：制造双极晶体管的方法
公开(公告)号：US4826780A
公开(公告)日：1989-05-02
申请号：US124423
申请日：1987-11-23
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092 , H01L21/38
CPC分类号： H01L27/0244 , H01L21/74 , H01L21/761 , H01L21/82285 , H01L27/0623 , H01L27/0826 , H01L27/0922 , Y10S148/009 , Y10S148/151
摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.
摘要翻译：在半导体IC中，通过在n型外延区域中形成例如p型集电极区域（39），形成具有均匀特性和高击穿电压的垂直pnp或npn晶体管，n阱基极形成在p型集电极区域（39）中的区域（41）和形成在n阱基极区域（41）中的p型发射极区域（42）。此外，例如如图1所示。如图9所示，p-区域（40）和（49）与p-集电极区域（39）同时形成，并且与n-阱基区域（41）同时形成n区域（53），从而构成 IIL具有优越的特性和高电阻器件，同时形成垂直晶体管而不大幅度增加制造步骤; 并且以类似的方式，通过将在上述同步步骤中形成的p区域和n区域与形成垂直晶体管，高hFE晶体管，高速垂直npn晶体管，可以在有限的制造步骤中形成器件，p沟道和/或n沟道MOS晶体管。

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