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    • 1. 发明授权
    • Method of manufacturing isolated semiconductor devices
    • 制造隔离半导体器件的方法
    • US4685198A
    • 1987-08-11
    • US758962
    • 1985-07-25
    • Kenji KawakitaNoboru NomuraToyoki Takemoto
    • Kenji KawakitaNoboru NomuraToyoki Takemoto
    • H01L21/762H01L21/763H01L29/06
    • H01L21/76264H01L21/762H01L21/763H01L21/76281H01L21/76283Y10S148/05Y10S148/115Y10S438/973
    • Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.
    • 公开了通过采用选择氧化技术(LOCOS技术)将晶体管完全隔离的方法。 更具体地,在{100}硅衬底的表面中形成垂直开口,并且由该表面和这些开口的一部分侧壁形成抗氧化膜。 相继地,通过用具有取向各向异性的蚀刻剂进行蚀刻,在开口的侧壁中以高精度形成凹痕。 通过使用抗氧化膜作为掩模进行氧化,从开口侧壁中的凹陷生长的氧化膜与从相邻凹坑生长的另一氧化膜连接。 因此,在与衬底电隔离的硅的有源区中形成的晶体管的寄生电容小,并且可以形成为小尺寸,使得其具有适合于VLSI的特征,即高速度,低功耗, 和可加工性的高密度集成。
    • 2. 发明授权
    • Fine pattern forming method
    • 精细图案形成方法
    • US5169494A
    • 1992-12-08
    • US742550
    • 1991-08-08
    • Kazuhiko HashimotoTaichi KoizumiKenji KawakitaNoboru Nomura
    • Kazuhiko HashimotoTaichi KoizumiKenji KawakitaNoboru Nomura
    • G03F7/039G03F7/09
    • G03F7/094G03F7/039
    • The present invention provides a method of forming a fine pattern comprising the steps of forming on a semiconductor substrate an organic polymer film and heat treating it, forming on the organic polymer film an inorganic film and heat treating it, forming on the inorganic film an electron beam resist film and heat treating it, drawing a pattern on the resist film, developing it to form a resist pattern, and etching the inorganic film and the organic polymer film using the resist pattern as a mask, wherein the improvement comprises using one substance selected from the group consisting of a polyphenylene sulfide, a derivative thereof, and a polymer represented by the formula (I): ##STR1## where n is a positive integer, for forming at least one of the organic polymer film and the electron beam resist film. According to the present invention, it is possible to prevent charging by incident electrons, thereby keeping free of field butting and reduction of overlay accuracy, and to form an accurate and vertical fine resist pattern.
    • 本发明提供一种形成精细图案的方法,包括以下步骤:在半导体衬底上形成有机聚合物膜并进行热处理,在有机聚合物膜上形成无机膜并进行热处理,在无机膜上形成电子 抗蚀剂膜并对其进行热处理,在抗蚀剂膜上绘制图案,将其显影以形成抗蚀剂图案,并使用抗蚀剂图案作为掩模蚀刻无机膜和有机聚合物膜,其中改进包括使用选择的一种物质 由聚苯硫醚,其衍生物和由式(I)表示的聚合物组成:其中n为正整数,用于形成至少一个有机聚合物膜和电子 光束抗蚀膜。 根据本发明,可以防止入射电子的充电,从而保持无间隙对接和降低覆盖精度,并形成精确和垂直的精细抗蚀剂图案。