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1. 发明授权

US4021836A Inverted heterojunction photodiode 失效
标题翻译：反相异质结光电二极管
公开(公告)号：US4021836A
公开(公告)日：1977-05-03
申请号：US566159
申请日：1976-04-12
申请人： Austin M. Andrews, II , John E. Clarke , Edward R. Gertner , Joseph T. Longo , Richard C. Eden
发明人： Austin M. Andrews, II , John E. Clarke , Edward R. Gertner , Joseph T. Longo , Richard C. Eden
IPC分类号： H01L27/146 , H01L31/0352 , H01L31/109 , H01L27/14 , H01L29/161
CPC分类号： H01L27/14649 , H01L31/035281 , H01L31/109 , H01L2224/45144 , H01L2224/48463 , H01L2224/73265 , Y02E10/50 , Y10S148/064 , Y10S148/115 , Y10S148/135
摘要： An inverted heterojunction photodiode for use as a laser detector sensitive to the 8 - 14 .mu.m portion of the infrared spectrum and operable above 77.degree. K. The diode structure comprises a PbTe substrate, a first buffer layer of a Pb.sub..90 Sn.sub..10 Te material on said substrate and a second active layer of a Pb.sub..80 Sn.sub..20 Te material on said buffer layer. The first and second layers are grown by liquid phase epitaxy.
摘要翻译：用作激光检测器的反相异质结光电二极管，用于对红外光谱的8-14μm部分敏感且可在77°K以上操作。二极管结构包括PbTe衬底，Pb.90Sn.10Te材料的第一缓冲层在所述衬底上和在所述缓冲层上的Pb.80Sn.20Te材料的第二有源层。第一层和第二层通过液相外延生长。

2. 发明授权

US3911559A Method of dielectric isolation to provide backside collector contact and scribing yield 失效
标题翻译：电介质隔离方法提供背面集电极接触和划线产量
公开(公告)号：US3911559A
公开(公告)日：1975-10-14
申请号：US42363173
申请日：1973-12-10
申请人： TEXAS INSTRUMENTS INC
发明人： BEAN KENNETH E , AKRIDGE ALBERT NEAL
IPC分类号： H01L21/00 , H01L21/74 , H01L21/762 , H01L21/764 , H01L29/00 , H01L29/04 , H01L21/304 , H01L21/306 , H01L21/36
CPC分类号： H01L29/045 , H01L21/00 , H01L21/743 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L29/00 , Y10S148/028 , Y10S148/051 , Y10S148/085 , Y10S148/115 , Y10S148/122 , Y10S438/928 , Y10S438/977
摘要： The disclosure relates to a method in bipolar technology of providing a back contact to the collector of a semiconductor device through a dielectrically isolated circuit to reduce saturation resistance and to provide a continuous region of single crystal semiconductor material extending through the entire slice to provide scribe lines extending entirely through the single crystal material to provide much higher scribing yields. The above is provided by depositing an oxide layer over a single crystal substrate and selectively removing portions of the oxide which will later be either scribe points or be positioned beneath the collector of the transistor to be formed. Semiconductor material is then deposited over the oxide layer, this material depositing on the oxide layer and also on the silicon substrate in the region where the oxide has been removed. A buildup will be provided which is polycrystalline over the oxide layer and single crystal over the region wherein the deposited silicon is directly in contact with the silicon substrate. The silicon substrate is then ground and polished back and an epitaxial layer is then deposited thereon. In the case of the scribe lines, an oxide coating is then placed over the topmost semiconductor layer and portions of the oxide are removed over the scribe lines. An orientation dependent etch is then provided through the semiconductor material bound to the scribe lines. Normal scribing techniques could also be used to provide a relatively high yield as compared with the prior art along the scribe lines.
摘要翻译：本公开涉及一种双极技术中的方法，其通过介电隔离电路向半导体器件的集电极提供背接触以降低饱和电阻并提供延伸穿过整个切片的单晶半导体材料的连续区域，以提供划线完全延伸通过单晶材料，以提供更高的划线产量。通过在单晶衬底上沉积氧化物层并选择性地去除氧化物的部分，这将随后被刻划或者被放置在待形成的晶体管的集电极之下来提供上述。然后将半导体材料沉积在氧化物层上，该材料沉积在氧化物层上，并且在氧化物被去除的区域中沉积在硅衬底上。将提供在氧化物层和在其上沉积的硅直接与硅衬底接触的区域上的单晶多晶的堆积。然后将硅衬底研磨并抛光，然后在其上沉积外延层。在划线的情况下，然后将氧化物涂层放置在最上面的半导体层上，并且氧化物的部分在划线上被去除。然后通过结合到划线的半导体材料提供取向相关的蚀刻。与沿着划线的现有技术相比，正常划线技术也可以用于提供相对高的产量。

3. 发明授权

US3878552A Bipolar integrated circuit and method 失效
标题翻译：双极集成电路和方法
公开(公告)号：US3878552A
公开(公告)日：1975-04-15
申请号：US30598372
申请日：1972-11-13
申请人： RODGERS THURMAN J
发明人： RODGERS THURMAN J
IPC分类号： H01L21/764 , H01L21/8222 , H01L27/00 , H01L29/06 , H01L19/00
CPC分类号： H01L29/0661 , H01L21/764 , H01L21/8222 , H01L27/00 , Y10S148/007 , Y10S148/025 , Y10S148/051 , Y10S148/085 , Y10S148/115 , Y10S148/138 , Y10S148/139 , Y10S148/168
摘要： An integrated circuit formed from starting material including a highly doped substrate of one conductivity type having crystallographic planes at one face thereof which etch preferentially, such as the or planes, and three layers of semiconductor material on said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped buried layer and another layer all of opposite conductivity type with a V-groove extending through said layers and into said substrate to define an island and a well within said island extending to a point adjacent said highly doped buried layer and a diffusion region formed in said well to provide connection to the buried layer together with additional regions formed in said island to define with said layers a bipolar semiconductor device. The method of forming bipolar semiconductor devices in integrated circuits which comprises processing a wafer including crystallographic planes at one face thereof which etch preferentially, such as the or planes, and three layers of semiconductor material on said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped buried layer and another layer of opposite conductivity type, masking the surface of the device to form a ring of predetermined width and an opening of predetermined size within said ring and thereafter etching to form a groove extending into the substrate and a well extending adjacent the highly doped buried layer and forming a diffusion region at the surface of the well to provide connection to the highly doped buried layer and additional steps of forming various regions to define bipolar semiconductor devices within said groove.
摘要翻译：由起始材料形成的集成电路包括一种具有一种导电类型的高度掺杂的衬底，其一面具有优先刻蚀的诸如100或110平面的结晶面以及所述一个面上的三层半导体材料，所述层包括轻掺杂或本征层，高度掺杂的掩埋层和全部具有相反导电类型的另一层，其中V沟槽延伸穿过所述层并进入所述衬底，以在所述岛内限定岛和井，延伸到邻近所述高掺杂掩埋层的点和在所述阱中形成的扩散区域，以与形成在所述岛中的附加区域一起提供与掩埋层的连接，以与所述层形成双极半导体器件。

4. 发明授权

US3818583A Method for fabricating semiconductor structure having complementary devices 失效
标题翻译：用于制备具有补充装置的半导体结构的方法
公开(公告)号：US3818583A
公开(公告)日：1974-06-25
申请号：US29167972
申请日：1972-09-25
申请人： SIGNETICS CORP
发明人： POLATA B
IPC分类号： H01L21/762 , H01L27/082 , B01J17/00
CPC分类号： H01L21/76297 , H01L27/0826 , Y10S148/05 , Y10S148/051 , Y10S148/085 , Y10S148/115
摘要： Method for fabricating a semiconductor structure having complementary devices in which islands of one conductivity are formed by a backside diffusion into a semiconductor body of opposite conductivity type to provide regions of first and second conductivities which are subsequently dielectrically isolated before the formation of the complementary devices therein.
摘要翻译：用于制造具有互补装置的半导体结构的方法，其中通过背面扩散形成一个导电性的岛，形成具有相反导电类型的半导体本体的第一和第二导电性的区域，其后在其互补装置形成之前被介电隔离。

5. 发明授权

US3770533A Method of producing high resolution patterns in single crystals 失效
标题翻译：在单晶中生产高分辨率图案的方法
公开(公告)号：US3770533A
公开(公告)日：1973-11-06
申请号：US3770533D
申请日：1971-07-02
申请人： PHILIPS CORP
发明人： ZWICKER W
IPC分类号： H01L21/00 , H01L21/033 , H01L21/288 , H01L21/308 , H01L7/50
CPC分类号： H01L21/3083 , H01L21/00 , H01L21/0334 , H01L21/288 , Y10S148/051 , Y10S148/115
摘要： A method of producing by etching, high resolution patterns in a single metal or metalloid crystal by electrolytic displacement of portions of the metal or metalloid crystal by a different metal through an apertured mask and subsequent removal of the different metals.
摘要翻译：通过使用不同的金属通过孔径掩模电解去除金属或准金属晶体的部分并随后除去不同的金属，通过蚀刻在单个金属或准金属晶体中蚀刻高分辨率图案的方法。

6. 发明授权

US3769562A Double isolation for electronic devices 失效
标题翻译：电子设备双重隔离
公开(公告)号：US3769562A
公开(公告)日：1973-10-30
申请号：US3769562D
申请日：1972-02-07
申请人： TEXAS INSTRUMENTS INC
发明人： BEAN K
IPC分类号： B41J2/34 , H01L21/00 , H01L21/306 , H01L21/762 , H01L23/29 , H01L27/02 , H01L29/00 , H01L29/04 , H01L7/00
CPC分类号： H01L29/045 , B41J2/34 , H01L21/00 , H01L21/30608 , H01L21/76297 , H01L23/29 , H01L23/291 , H01L27/0211 , H01L29/00 , H01L2924/0002 , H01L2924/3011 , Y10S148/043 , Y10S148/051 , Y10S148/085 , Y10S148/115 , Y10S148/135 , Y10S148/136 , H01L2924/00
摘要： A thermally and electrically isolated array of islands or mesas of semiconductor material and method of fabrication are provided wherein each island or mesa is surrounded by moats formed by either orientation-dependent etching or, space permitting, by standard multiple-dependent techniques. These moats have a ''''W''''shaped cross-section surrounding each island or mesa. Such an array of islands or mesas is especially adapted for use in the fabrication of high voltage or high power integrated circuit devices, and thermal print heads.
摘要翻译：提供了一种热和电隔离的半导体材料的岛或台面阵列和制造方法，其中每个岛或台面由通过取向依赖蚀刻形成的护城河或通过标准多重依赖技术在空间允许下包围。这些护城河围绕每个岛屿或台面都有一个“W”形横截面。这种岛状或台面阵列特别适用于制造高压或高功率集成电路器件和热敏打印头。

7. 发明授权

US3765969A Precision etching of semiconductors 失效
标题翻译：精密蚀刻半导体
公开(公告)号：US3765969A
公开(公告)日：1973-10-16
申请号：US3765969D
申请日：1970-07-13
申请人： BELL TELEPHONE LABOR INC
发明人： KRAGNESS R , WAGENER H
IPC分类号： G02B6/36 , H01L21/00 , H01L21/306 , H01L7/00 , C09K3/00 , G03C5/00
CPC分类号： H01L21/30608 , G02B6/3692 , H01L21/00 , Y10S148/051 , Y10S148/085 , Y10S148/102 , Y10S148/115 , Y10S148/118
摘要： A method of precision etching for semiconductor device fabrication using the preferential characteristics of certain etchants for particular crystallographic planes of monocrystalline material. In particular, silicon is precisely etched by disposing etch masks on surfaces parallel to the (100) plane with the mask edges parallel to the lines of intersection of the (111) planes with the (100) plane, and using alkali hydroxide etches as well as certain organic reagents, which have substantially lower etch rates with respect to the (110) and (111) planes. Also, undercutting at intersections of the mask boundaries which expose the (110) plane is avoided by shaping the mask to compensate therefor. A suitable etchant formulation contains 50 parts by volume of water, 15 parts by volume of npropanol and has molar concentration of hydroxide of about 5.3.
摘要翻译：一种用于半导体器件制造的精密蚀刻方法，其使用某些特定蚀刻剂对于单晶材料的特定晶面的优先特性。特别地，通过在与（100）平面平行的表面上设置蚀刻掩模来精确地蚀刻硅，掩模边缘平行于（111）面与（100）面的相交线，以及使用碱金属氢氧化物蚀刻作为某些有机试剂，其相对于（110）和（111）面具有相当低的蚀刻速率。此外，通过对掩模进行成形来补偿曝光（110）面的掩模边界的交点处，可以避免底切。合适的蚀刻剂配方含有50体积份的水，15体积份的正丙醇，并且氢氧化物的摩尔浓度为约5.3。

8. 发明授权

US3746587A Method of making semiconductor diodes 失效
标题翻译：制造半导体二极管的方法
公开(公告)号：US3746587A
公开(公告)日：1973-07-17
申请号：US3746587D
申请日：1970-11-04
申请人： RAYTHEON CO
发明人： ROSVOLD W
IPC分类号： H01L21/306 , H01L21/3065 , H01L21/308 , H01L29/00 , H01L7/36 , H01L3/00 , H01L7/00
CPC分类号： H01L21/3086 , H01L21/30608 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L29/00 , Y10S148/051 , Y10S148/054 , Y10S148/085 , Y10S148/115 , Y10S148/145 , Y10S438/977 , Y10S438/978
摘要： A METHOD OF MAKING A NUMBER OF SEMICONDUCTOR DIODES ON A SINGLE WATER WITHOUT BREAKAGE DURING HANDLING AND PROCESSING, COMPRISING THE STEPS OF FORMING A PLURALITY OF MESAS ON ONE SURFACE OF AN INTRINSIC SUBSTRATE, DIFFUSING A SELECTED FIRST CONDUCTIVITY-TYPE REGION INTO EACH MESA, COATING THE FRONT SURFACE OF THE SUBBSTRATE AND MESAS WITH OXIDE, CHEMICALLY MILLING RECESSES INTO THE OPPOSITE SIDE OF THE SUBSTRATE IN ALIGNMENT WITH THE MESAS TO A PREDETERMINED DEPTH WHERE THE MESAS ARE EACH SUPPROTED BY A THIN ANNULAR AREA OF SUBSTRATE MATERIAL PERMITTING TRANSFER OF THE DEVICE INTO AN EPITAXIAL REACTOR, GAS ETCHING THE RECESSES TO A DEPTH BEYOND THE OXIDE INTERFACE TO PHYSICALLY SEPARATE THE MESAS FROM THE SUBSTRATE MATERIAL, GROWING A THIN EPITAXIAL LAYER OF OPPOSITE CONDUCTIVITY TYPE OVER THE BACK SURFACE OF THE DEVICE, APPLYING OHMIC CONTACTS TO THE DEVICE, AND SEPARATING THE INDIVIDUAL MESAS.

9. 发明授权

US3742315A Schottky barrier type semiconductor device with improved backward breakdown voltage characteristic 失效
标题翻译：具有改进背后断开电压特性的肖特基阻挡型半导体器件
公开(公告)号：US3742315A
公开(公告)日：1973-06-26
申请号：US3742315D
申请日：1971-10-18
申请人： MATSUSHITA ELECTRONICS CORP
发明人： KANO G , HASEGAWA H , IIZUKA M , FUJIWARA S , TERAMOTO I , IWASA H
IPC分类号： H01L21/306 , H01L23/485 , H01L29/00 , H01L29/872 , H01L5/02 , H01L7/50 , H01L7/60
CPC分类号： H01L29/872 , H01L21/30608 , H01L23/4855 , H01L29/00 , H01L2924/0002 , Y10S148/051 , Y10S148/102 , Y10S148/115 , Y10S148/139 , H01L2924/00
摘要： A semiconductor device having a Schottky barrier junction formed in the bottom of a polygonal recess on a surface of a semiconductor substrate comprises an undercut in the recess beneath an insulating mask formed on the substrate, and a metal passing through the mask and extending to the bottom of the recess for forming said junction. The undercut provides an enclosed spacing encircling the junction portion of said metal and said semiconductor, thereby improving the backward breakdown voltage characteristic therein.

10. 发明授权

US3698944A Method of obtaining phased growth of epitaxial layers 失效
标题翻译：获得外延层的相变生长的方法
公开(公告)号：US3698944A
公开(公告)日：1972-10-17
申请号：US3698944D
申请日：1970-06-15
申请人： TEXAS INSTRUMENTS INC
发明人： DYER LAWRENCE DEAN
IPC分类号： C30B29/00 , B01J17/28
CPC分类号： C30B29/00 , Y10S148/115 , Y10S148/15 , Y10S438/967
摘要： DISCLOSED IS A METHOD OF PREPARING SUBSTRATES THAT HAVE POSITIONS AT WHICH NUCLEATION PREFERENTIALLY TAKES PLACE DURING EPITAXIAL DEPOSITION OF A MATERIAL HAVING A SUBSTANTIALLY DIFFEENT CRYSTAL LATTICE STRUCTURE THAN THE SUBSTRATE MATERIAL. A SUBSTRATE, ORIENTED TO PRESENT A PRESELECTED LOW INDEX REFERENCE CRYSTAL PLANE, IS CUT ALONG A PLANE HAVING A PRESELECTED ANGLE OF INCLINATION TO THE LOW INDEX CRYSTAL PLANE, THE AXIS OF INCLINATION ALSO HAVING A PRESELECTED ANGLE WITH A DIRECTION OF CLOSE-PACKED ATOMS IN THE LOW INDEX CRYSTAL PLANE. THESE PRESELECTED ANGLES ARE SO CHOSEN THAT CRYSTAL STEPS AND KNICKS ARE FORMED IN PRESELECTED POSITIONS ALONG THE SURFACE OF THE SUBSTRATE. SINCE NUCLEI PREFERENTIALLY FORM AT KINKS AND CRYSTAL STEPS, PROPER SELECTION OF THE CUTTING PLANE ENABLES CONTROL OF THE LOCATION OF NUCLEI WHICH ARE SUBSTANTIALLY IN PHASE WITH ONE ANOTHER ACROSS THE SUBSTRATE SURFACE.

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