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1. 发明授权

US5066602A Method of making semiconductor IC including polar transistors 失效
标题翻译：制造包含极性晶体管的半导体IC的方法
公开(公告)号：US5066602A
公开(公告)日：1991-11-19
申请号：US295380
申请日：1989-01-10
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092
CPC分类号： H01L27/0244 , H01L21/74 , H01L21/761 , H01L21/82285 , H01L27/0623 , H01L27/0826 , H01L27/0922 , Y10S148/009 , Y10S148/151
摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

2. 发明授权

US4459496A Semiconductor integrated circuit having stacked integrated injection logic circuits 失效
标题翻译：具有层叠集成注入逻辑电路的半导体集成电路
公开(公告)号：US4459496A
公开(公告)日：1984-07-10
申请号：US251966
申请日：1981-04-03
申请人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
发明人： Haruyasu Yamada , Toyoki Takemoto , Tadao Komeda , Tsutomu Fujita , Yuichi Hirofuji , Hiroyuki Sakai
IPC分类号： H03K19/091 , H03K19/092
CPC分类号： H03K19/091
摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.
摘要翻译：在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。

3. 发明授权

US5661066A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5661066A
公开(公告)日：1997-08-26
申请号：US965967
申请日：1991-04-02
申请人： Toyoki Takemoto , Haruyasu Yamada , Tsutomu Fujita , Tadao Komeda
发明人： Toyoki Takemoto , Haruyasu Yamada , Tsutomu Fujita , Tadao Komeda
IPC分类号： H01L21/8222 , H01L27/02 , H01L27/06 , H01L29/8605 , H01L29/93 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/0233 , H01L21/8222 , H01L27/0244 , H01L27/0647 , H01L29/8605 , H01L29/93
摘要： In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.
摘要翻译：在包括IIL和高频npn双极晶体管的集成电路中，其具有用于其反相npn输出晶体管的深p型基极区45，电路元件如电阻器部分R，电容器部分C，二极管部分D 并且隔离交叉连接部分Cr设置有与IIL中的p型区域45同时形成的深P型区域54,54'，65'，71和82，从而可靠性的电路元件及其特性得到改善，从而进一步提高了制造成品率。

4. 发明授权

US4826780A Method of making bipolar transistors 失效
标题翻译：制造双极晶体管的方法
公开(公告)号：US4826780A
公开(公告)日：1989-05-02
申请号：US124423
申请日：1987-11-23
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Tsutomu Fujita
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092 , H01L21/38
CPC分类号： H01L27/0244 , H01L21/74 , H01L21/761 , H01L21/82285 , H01L27/0623 , H01L27/0826 , H01L27/0922 , Y10S148/009 , Y10S148/151
摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.
摘要翻译：在半导体IC中，通过在n型外延区域中形成例如p型集电极区域（39），形成具有均匀特性和高击穿电压的垂直pnp或npn晶体管，n阱基极形成在p型集电极区域（39）中的区域（41）和形成在n阱基极区域（41）中的p型发射极区域（42）。此外，例如如图1所示。如图9所示，p-区域（40）和（49）与p-集电极区域（39）同时形成，并且与n-阱基区域（41）同时形成n区域（53），从而构成 IIL具有优越的特性和高电阻器件，同时形成垂直晶体管而不大幅度增加制造步骤; 并且以类似的方式，通过将在上述同步步骤中形成的p区域和n区域与形成垂直晶体管，高hFE晶体管，高速垂直npn晶体管，可以在有限的制造步骤中形成器件，p沟道和/或n沟道MOS晶体管。

5. 发明授权

US4233615A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4233615A
公开(公告)日：1980-11-11
申请号：US933045
申请日：1978-08-10
申请人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Michihiro Inoue
发明人： Toyoki Takemoto , Tadao Komeda , Haruyasu Yamada , Michihiro Inoue
IPC分类号： H01L29/80 , H01L21/337 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/78 , H01L29/808
CPC分类号： H01L29/78 , H01L29/808
摘要： An IC device comprising a junction type field effect transistor of a back gate type and a bipolar device such as a bipolar transistor and a resistor made of impurity diffused region, wherein an extremely thin (in the order of 0.05-0.2 .mu.m) impurity doped surface region of a conductivity type same as that of a back gate region is formed at the surface of a surface channel region, and is separated from at least a drain region to sustain high breakdown voltage between gate region and the drain region; the impurity surface region serving to reduce noise and also enabling to achieve satisfactory characteristics of J-FET and also good ohmic characteristics of the resistor.
摘要翻译：一种IC器件，包括背栅型的结型场效应晶体管和双极晶体管的双极器件和由杂质扩散区域制成的电阻器，其中极薄（约0.05-0.2μm）的杂质掺杂在表面沟道区域的表面形成与背栅极区域相同的导电类型的表面区域，并且至少从漏极区域分离以维持栅极区域与漏极区域之间的高的击穿电压; 杂质表面区域用于降低噪声，并且还能够实现令人满意的J-FET特性和电阻器的良好欧姆特性。

6. 发明授权

US4484211A Oxide walled emitter 失效
标题翻译：氧化物壁发射体
公开(公告)号：US4484211A
公开(公告)日：1984-11-20
申请号：US542555
申请日：1983-10-17
申请人： Toyoki Takemoto , Tsutomu Fujita , Hiroyuki Sakai , Haruyasu Yamada
发明人： Toyoki Takemoto , Tsutomu Fujita , Hiroyuki Sakai , Haruyasu Yamada
IPC分类号： H01L29/06 , H01L29/732 , H01L27/04 , H01L29/04 , H01L29/72
CPC分类号： H01L29/7325 , H01L29/0649
摘要： A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.
摘要翻译：一种半导体集成电路器件，其中氧化物隔离双极晶体管的发射极的侧表面被绝缘化合物或区域包围，使得发射极和基极之间的电容降低，并且通过自对准形成基极，活性碱在外部碱基和发光体之间的影响可以忽略不计。因此，基极电阻和寄生电容降低。

7. 发明授权

US4441198A Shift register circuit 失效
标题翻译：移位寄存器电路
公开(公告)号：US4441198A
公开(公告)日：1984-04-03
申请号：US275848
申请日：1981-06-22
申请人： Jun Shibata , Haruyasu Yamada , Toshiki Mori , Toyoki Takemoto
发明人： Jun Shibata , Haruyasu Yamada , Toshiki Mori , Toyoki Takemoto
IPC分类号： G11C19/00 , H03M1/00 , G11C19/28 , H03K19/173
CPC分类号： G11C19/00 , H03M1/38
摘要： A first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.
摘要翻译：第一逻辑电路包括耦合由不同相位的时钟脉冲驱动的门电路，经由耦合门电路级联的触发器电路和用于将触发器电路的输出反馈到前级触发电路的反馈电路并产生不同相位的脉冲序列。第二逻辑电路还包括由用于由第一逻辑电路产生的脉冲序列驱动的每个触发器电路的锁存电路。这些逻辑电路对逐次逼近A / D转换器的逐次逼近寄存器是有用的。

8. 发明授权

US4417233A Fully parallel threshold type analog-to-digital converter 失效
标题翻译：全并联门限类型模数转换器
公开(公告)号：US4417233A
公开(公告)日：1983-11-22
申请号：US123646
申请日：1980-02-22
申请人： Michihiro Inoue , Toyoki Takemoto , Haruyasu Yamada
发明人： Michihiro Inoue , Toyoki Takemoto , Haruyasu Yamada
IPC分类号： H03M1/00 , H03K13/03
CPC分类号： H03M1/361
摘要： A parallel type A/D converter capable of operating at an extremely high speed with a high degree of accuracy and with low power consumption. A plurality of comparators each having a reference voltage corresponding to an assigned quantizing level are disposed in parallel with each other and divided into a plurality of comparator blocks or groups. A plurality of sub-comparators are provided so that prior to the comparison of the input signal by the comparators, the input signal is first compared with the reference voltages of the sub-comparators and in response to the output from the sub-comparator having the reference voltage comparable or corresponding to the incoming input signal, only the comparators in the comparator block or group associated with said sub-comparator are energized or enabled while the remaining comparators are kept de-energized or disabled, whereby a minimum power consumption may be attained.
摘要翻译：一种并联型A / D转换器，能够以极高的精度和低功耗运行。每个具有与分配的量化电平相对应的参考电压的多个比较器彼此并联设置并分成多个比较器块或组。提供多个子比较器，使得在比较器比较输入信号之前，首先将输入信号与子比较器的参考电压进行比较，并且响应于具有该比较器的子比较器的输出与输入输入信号相当或对应的参考电压，只有与所述子比较器相关联的比较器块或组中的比较器通电或使能，而剩余的比较器保持断电或禁用，从而可以获得最小的功率消耗。

9. 发明授权

US4563227A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4563227A
公开(公告)日：1986-01-07
申请号：US660255
申请日：1984-10-12
申请人： Hiroyuki Sakai , Kenji Kawakita , Tsutomu Fujita , Toyoki Takemoto
发明人： Hiroyuki Sakai , Kenji Kawakita , Tsutomu Fujita , Toyoki Takemoto
IPC分类号： H01L21/762 , H01L21/38 , H01L21/467
CPC分类号： H01L21/76232 , H01L21/762
摘要： The invention provides a method for manufacturing a semiconductor device, wherein a semiconductor substrate is vertically etched to form a groove, antioxidant insulating films are formed on the side walls of the groove, and local oxidation is performed. Lateral extrusion of an oxide film which is a so-called bird's beak and a projection of the oxide film which is a so-called bird's head are substantially eliminated. As a result, the active region of the transistor, that is, the element formation region may not be narrowed, providing high packing density and high precision. Furthermore, the surface of the semiconductor substrate is flattened to prevent short-circuiting and disconnections of wiring layers. Stable manufacturing process provides a high yield of the semiconductor device. Electrical characteristics of the semiconductor device are greatly improved.
摘要翻译：本发明提供一种制造半导体器件的方法，其中半导体衬底被垂直蚀刻以形成沟槽，在沟槽的侧壁上形成抗氧化绝缘膜，并进行局部氧化。基本上消除了所谓的鸟喙的氧化膜的侧向挤出和所谓的鸟头的氧化膜的突起。结果，晶体管的有源区，即元件形成区域可能不会变窄，提供高的堆积密度和高精度。此外，半导体衬底的表面被平坦化以防止布线层的短路和断开。稳定的制造工艺提供了高产量的半导体器件。半导体器件的电气特性大大提高。

10. 发明授权

US4563807A Method for making semiconductor device utilizing molecular beam epitaxy to form the emitter layers 失效
标题翻译：制造半导体器件利用分子束外延形成发射极层的方法
公开(公告)号：US4563807A
公开(公告)日：1986-01-14
申请号：US596592
申请日：1984-04-04
申请人： Hiroyuki Sakai , Toyoki Takemoto , Kenji Kawakita , Tsutomu Fujita , Atsuko Akiyama
发明人： Hiroyuki Sakai , Toyoki Takemoto , Kenji Kawakita , Tsutomu Fujita , Atsuko Akiyama
IPC分类号： H01L21/20 , H01L21/203 , H01L21/285 , H01L21/331 , H01L29/73 , H01L29/732 , H01L21/225
CPC分类号： H01L29/7325 , H01L21/02532 , H01L21/02576 , H01L21/02631 , H01L21/28525 , Y10S148/123 , Y10S148/124 , Y10S148/169
摘要： Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.
摘要翻译：诸如双极晶体管的半导体器件通过分子束外延制造，其中发射极层（27）和多晶硅的覆盖接触区域（28）在硅衬底（23 + 26）上连续生长而不破坏高真空，因此消除多晶硅层（28）下的自然氧化膜的不利界面和不利的供体 - 受体补偿，同时实现良好控制的hFE并实现浅发射极结。

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