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1. 发明授权

US5455955A Data processing system with device for arranging instructions 失效
标题翻译：数据处理系统，用于安排指令
公开(公告)号：US5455955A
公开(公告)日：1995-10-03
申请号：US951772
申请日：1992-09-28
申请人： Hiroyuki Kida , Hideo Maejima , Ikuro Masuda , Shirou Baba
发明人： Hiroyuki Kida , Hideo Maejima , Ikuro Masuda , Shirou Baba
IPC分类号： G06F15/00 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/42 , G06F9/45 , G06F9/46 , G06F9/26 , G06F9/32
CPC分类号： G06F9/462 , G06F8/41 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30196 , G06F9/3814 , G06F9/3851 , G06F9/4426
摘要： A data processing system incorporating a main memory for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory. The system translates an instruction word read out of the main memory into an intermediate machine word having the orthogonal format, and addresses a microprogram memory in correspondence to the instruction word by analyzing the intermediate machine word. The system further incorporates a plurality of register sets so that each different task can use an individual register set, and a memory for memorizing the number of registers holding parameters used commonly among procedures corresponding to the register sets, so that the number of registers for each use can be changed arbitrarily for each register set by using the memory.
摘要翻译：一种数据处理系统，包括用于存储指令和操作数的主存储器，并且响应于从主存储器读出的指令，以微程序控制系统的模式执行数据处理。该系统将从主存储器读出的指令字转换为具有正交格式的中间机器字，并通过分析中间机器字来对应于指令字寻址微程序存储器。该系统还包括多个寄存器组，使得每个不同的任务可以使用单个寄存器组，以及存储器，用于存储保持与寄存器组相对应的过程中共同使用的参数的寄存器的数量，使得每个寄存器的寄存器数量通过使用存储器可以为每个寄存器设置任意使用。

2. 发明授权

US4979103A Data processing method and apparatus having plural bus interfaces 失效
标题翻译：具有多个总线接口的数据处理方法和装置
公开(公告)号：US4979103A
公开(公告)日：1990-12-18
申请号：US176234
申请日：1988-03-31
申请人： Hiroyuki Kida , Tooru Komagawa , Hideo Maejima
发明人： Hiroyuki Kida , Tooru Komagawa , Hideo Maejima
IPC分类号： G06F9/30 , G06F15/78
CPC分类号： G06F15/786
摘要： A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.
摘要翻译：一种用于控制系统中的多个总线接口的方法和装置，包括在一个芯片上的中央处理单元和内部存储器。当鉴别位于芯片外部的一个操作数时，由第一操作数检索单元执行第一操作数检索操作，并且当鉴别位于芯片内的另一操作数时，由第二操作数检索单元执行第二操作数检索操作，使得操作数根据第一和第二操作数检索单元的总线接口信号读取到中央处理单元。

3. 发明授权

US4835679A Microprogram control system 失效
标题翻译：微程序控制系统
公开(公告)号：US4835679A
公开(公告)日：1989-05-30
申请号：US818685
申请日：1986-01-14
申请人： Hiroyuki Kida , Hideo Maejima
发明人： Hiroyuki Kida , Hideo Maejima
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/26 , G06F9/261
摘要： Micro instructions having a predetermined relationship with respect to each other are modified so that an original micro instruction and address assigned thereto can be restored by combining one or more modified micro instructions and address assigned thereto. A microprogram memory stores the micro instructions in such a modified form and at the modified address. When an original address is designated, one or more term lines are activated in a decoder of the microprogram memory, and modified micro instructions corresponding to the activated term lines are read-out from a memory array of the microprogram memory. The read modified micro instructions are logically combined to restore the original micro instruction. Thereby, the number of micro instructions to be actually stored in the microprogram memory can be reduced.
摘要翻译：修改相对于彼此具有预定关系的微指令，使得可以通过组合一个或多个修改的微指令和分配给其的地址来恢复分配给其的原始微指令和地址。微程序存储器以这种修改的形式和修改的地址存储微指令。当指定原始地址时，在微程序存储器的解码器中激活一个或多个术语行，并且从微程序存储器的存储器阵列中读出对应于激活的术语行的修改的微指令。读取修改的微指令逻辑组合以恢复原始微指令。由此，可以减少实际存储在微程序存储器中的微指令的数量。

4. 发明授权

US4740892A Microcomputer having peripheral functions 失效
标题翻译：微电脑具有外围功能
公开(公告)号：US4740892A
公开(公告)日：1988-04-26
申请号：US760180
申请日：1985-07-29
申请人： Hiroyuki Kida , Hideo Maejima
发明人： Hiroyuki Kida , Hideo Maejima
IPC分类号： G06F1/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F9/3851 , G06F13/28 , G06F15/7832 , G06F9/268
摘要： On a single semiconductor chip, there are provided an arithmetic logic unit, a general-purpose register for storing data to be processed and data as a result of the operation in the arithmetic logic unit, a peripheral register used for performing the peripheral functions required, a buffer register and an internal bus line through which the above mentioned components conduct the data communication with one another. Further, there is provided on the chip a microprogram storage and control device which stores microinstructions for processing instructions read out from a main memory (an instruction processing) and data processing necessary for performing the required peripheral functions (an auxiliary function processing). The microinstructions are read out successively and decoded one after another to produce control signals for controlling the arithmetic logic unit, the general-purpose register, the peripheral register and the buffer register, whereby these components are shared by the instruction processing and the auxiliary function processing.
摘要翻译：在单个半导体芯片上，提供了一种算术逻辑单元，用于存储待处理数据的通用寄存器和作为算术逻辑单元中的操作的结果的数据，用于执行所需外围功能的外设寄存器，缓冲寄存器和内部总线，上述组件通过该总线彼此进行数据通信。此外，在芯片上设置有微程序存储和控制装置，其存储用于处理从主存储器读出的指令的微指令（指令处理）以及用于执行所需的外围功能（辅助功能处理）所需的数据处理。连续读出微指令，逐个解码，生成用于控制算术逻辑单元，通用寄存器，外设寄存器和缓冲寄存器的控制信号，由此通过指令处理和辅助功能处理共享这些元件。

5. 发明授权

US5524087A Method of forming a signal wave from first and second waveform data 失效
标题翻译：从第一和第二波形数据形成信号波的方法
公开(公告)号：US5524087A
公开(公告)日：1996-06-04
申请号：US367596
申请日：1995-01-03
申请人： Masanobu Kawamura , Hiroyuki Kida , Seiji Kamada , Toshiyuki Tojo , Takeshi Ohkubo , Hiroyuki Matsuura , Naoki Yashiki , Nobuo Shibasaki
发明人： Masanobu Kawamura , Hiroyuki Kida , Seiji Kamada , Toshiyuki Tojo , Takeshi Ohkubo , Hiroyuki Matsuura , Naoki Yashiki , Nobuo Shibasaki
IPC分类号： H03B28/00 , G06F1/035 , H03K3/78 , H03K4/02 , H03K4/92 , H04L29/10 , G06F1/02
CPC分类号： G06F1/035
摘要： A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.
摘要翻译：提供了一种产生各种波形（例如，正弦波，三角波或梯形波）和各种频率的信号的可变波形成电路。提供了存储关于波形的波形信息的随机存取存储器（存储装置）121。根据存储在存储装置中的波形信息，控制增量/减量电路123中的数字值的更新或保持，并且通过数字/模拟（D / A）转换对数字值进行数/模转换电路124由包括增量/递减电路123的数字值控制装置控制。通过将适当的波形形成信息写入存储装置，可以产生所需波形的信号。

6. 发明授权

US06169794A Method and apparatus for synchronizing databases within intelligent network 失效
标题翻译：在智能网络内同步数据库的方法和装置
公开(公告)号：US06169794A
公开(公告)日：2001-01-02
申请号：US09078259
申请日：1998-05-13
申请人： Kiyoshi Oshimi , Hiroyuki Kida , Masaki Watanabe , Shinichi Kozuka
发明人： Kiyoshi Oshimi , Hiroyuki Kida , Masaki Watanabe , Shinichi Kozuka
IPC分类号： H04M342
CPC分类号： H04Q3/0029 , H04M3/12 , H04M3/4228 , H04M7/06 , H04M2207/12 , Y10S707/99931
摘要： In an IN where the same service is provided by a plurality of SCPs, data consistency is maintained when an update occurs to subscriber data as a result of processing a service for a subscriber. When an update is made to a subscriber database in an SCP, update information is sent to the other SCPs by way of a route selected from among a route via a common channel signaling network, a route via a LAN, and a route via an SMS. Updates occurring during backup or restore processing on a main subscriber database in the SMS are accumulated within the SMS, and the accumulated updates are applied to the main subscriber database after completion of the processing.
摘要翻译：在由多个SCP提供相同服务的IN中，作为处理用户服务的结果对用户数据进行更新时，维持数据一致性。当对SCP中的用户数据库进行更新时，通过经由公共信道信令网络的路由，经由LAN的路由和经由SMS的路由，通过选择的路由将更新信息发送到其他SCP 。在SMS中的主用户数据库的备份或恢复处理期间发生的更新被存储在SMS内，并且在完成处理之后累积的更新被应用于主用户数据库。

7. 发明授权

US5631858A System for obtaining strict solution in accordance with accuracy of approximate solutions 失效
标题翻译：根据近似解决方案的准确度获得严格解决方案的系统
公开(公告)号：US5631858A
公开(公告)日：1997-05-20
申请号：US89103
申请日：1993-08-12
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

8. 发明授权

US08391867B2 Base station apparatus and neighboring cell information management method 失效
公开(公告)号：US08391867B2
公开(公告)日：2013-03-05
申请号：US12320255
申请日：2009-01-22
申请人： Hiroyuki Kida , Hiroshi Ohiwane
发明人： Hiroyuki Kida , Hiroshi Ohiwane
IPC分类号： H04W36/00
CPC分类号： H04W36/0083
摘要： A first base station apparatus, when newly installed, extracts cells of a second base station apparatus and its coverage cells neighboring them from neighboring cell information stored therein. The first base station apparatus notifies the second base station apparatus of the cells by a notification message. The second base station apparatus updates neighboring cell information stored therein based on the notification message. The first base station apparatus also sends a notification message to a third base station apparatus so that the third base station apparatus updates neighboring cell information stored therein.

9. 发明申请

US20090280811A1 Base station apparatus and neighboring cell information management method 失效
标题翻译：基站装置及相邻小区信息管理方法
公开(公告)号：US20090280811A1
公开(公告)日：2009-11-12
申请号：US12320255
申请日：2009-01-22
申请人： Hiroyuki Kida , Hiroshi Ohiwane
发明人： Hiroyuki Kida , Hiroshi Ohiwane
IPC分类号： H04W36/00 , H04M1/00
CPC分类号： H04W36/0083
摘要： A first base station apparatus, when newly installed, extracts cells of a second base station apparatus and its coverage cells neighboring them from neighboring cell information stored therein. The first base station apparatus notifies the second base station apparatus of the cells by a notification message. The second base station apparatus updates neighboring cell information stored therein based on the notification message. The first base station apparatus also sends a notification message to a third base station apparatus so that the third base station apparatus updates neighboring cell information stored therein.
摘要翻译：第一基站装置当新安装时，从存储在其中的相邻小区信息中提取第二基站装置的小区和与其相邻的覆盖小区。第一基站装置通过通知消息向第二基站装置通知小区。第二基站装置基于通知消息更新存储在其中的相邻小区信息。第一基站装置还向第三基站装置发送通知消息，使得第三基站装置更新存储在其中的相邻小区信息。

10. 发明授权

US5642499A Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system 失效
标题翻译：用于控制处理器系统中的保存和恢复操作的执行时序的方法和装置
公开(公告)号：US5642499A
公开(公告)日：1997-06-24
申请号：US223834
申请日：1994-04-06
申请人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
发明人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F11/28 , G06F15/16 , G06F15/177
CPC分类号： G06F9/461 , G06F9/30025 , G06F9/3861 , G06F9/3885
摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.
摘要翻译：在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令的当前命令，如果当前命令是一个短命令。基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。

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