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1. 发明授权

US5631858A System for obtaining strict solution in accordance with accuracy of approximate solutions 失效
标题翻译：根据近似解决方案的准确度获得严格解决方案的系统
公开(公告)号：US5631858A
公开(公告)日：1997-05-20
申请号：US89103
申请日：1993-08-12
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

2. 发明授权

US5956263A Multiplication, division and square root extraction apparatus 失效
标题翻译：乘法，除法和平方根提取仪
公开(公告)号：US5956263A
公开(公告)日：1999-09-21
申请号：US797653
申请日：1997-01-31
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

3. 发明授权

US5293558A Multiplication, division and square root extraction apparatus 失效
标题翻译：乘法，除法和平方根提取仪
公开(公告)号：US5293558A
公开(公告)日：1994-03-08
申请号：US536565
申请日：1990-07-03
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： PCT No.PCT / JP89 / 01134 Sec。 371日期1990年7月3日 102（e）日期1990年7月3日PCT提交1989年11月2日PCT公布。出版物WO90 / 05335 日期1990年5月17日。一种乘法，除法和平方根提取装置，其通过使用迭代近似来计算加法，除法和平方根提取函数的解，具有连接到a的规定位宽的乘法器，加法器 - 减法器和移位器总线。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

4. 发明授权

US5841963A Dual information processing system having a plurality of data transfer channels 失效
标题翻译：双信息处理系统具有多个数据传输通道
公开(公告)号：US5841963A
公开(公告)日：1998-11-24
申请号：US861471
申请日：1997-05-21
申请人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
发明人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
IPC分类号： G06F11/16 , G06F15/17
CPC分类号： G06F11/1658
摘要： A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.
摘要翻译：由由多个数据传送单元连接的两个计算机系统和用于存储器副本的多个数据传送通道组成的双计算机系统，使得在从故障恢复时再次同步计算机系统。当数据传输通道没有发生故障时，数据传输单元在存储器复制操作中共享数据传输的负载，并且当在存储器复制操作期间在任何数据传送单元发生故障时，使用剩余的正常数据传送单元再次传送数据，从而高速地进行存储器复制，以便在从故障恢复时再次同步计算机系统，并且提高从故障恢复时的系统可靠性。

5. 发明授权

US07558483B2 Optical communication method, optical linking device and optical communication system 失效
标题翻译：光通信方法，光连接装置和光通信系统
公开(公告)号：US07558483B2
公开(公告)日：2009-07-07
申请号：US10897074
申请日：2004-07-23
申请人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
发明人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
IPC分类号： H04B10/00
CPC分类号： H04B10/271 , G06F13/4022 , H04B10/27 , H04B10/278
摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.
摘要翻译：该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为使总线同时由多个节点驱动。虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。

6. 发明申请

US20080170809A1 IMAGE PROCESSING SYSTEM WITH AN ADDRESS SNOOPING APPARATUS 失效
标题翻译：具有地址单元的图像处理系统
公开(公告)号：US20080170809A1
公开(公告)日：2008-07-17
申请号：US11971942
申请日：2008-01-10
申请人： Tetsuaki Nakamikawa , Shoji Muramatsu
发明人： Tetsuaki Nakamikawa , Shoji Muramatsu
IPC分类号： G06K9/54
CPC分类号： G06T1/20
摘要： An image processing system includes a first image processor that reads out a first image written in a main memory to apply a first process to the first image and write in the main memory as a second image, a second image processor that reads out a second image written in the main memory to apply a second process to the second image and write in the main memory as a second image, and an address snooping apparatus that snoops an address of the image written in the main memory to start the first process when the address is indicated to a previously set first value and start the second process when the address is indicated to a previously set second value, effectively enabling synchronization between a process by a CPU or a special purpose processor and a data delivery/receipt process between pipeline stages.
摘要翻译：一种图像处理系统包括：第一图像处理器，其读出写入主存储器中的第一图像以对第一图像应用第一处理，并将第二图像写入主存储器;第二图像处理器，读出第二图像写入主存储器中以对第二图像应用第二处理并将其写入主存储器中作为第二图像，以及地址窥探装置，其在写入主存储器中的图像的地址开始第一处理时，当地址被指示为先前设置的第一值并且当地址被指示为先前设置的第二值时开始第二处理，有效地实现CPU或专用处理器的处理与流水线级之间的数据传送/接收处理之间的同步。

7. 发明授权

US06782202B2 Optical communication method, optical linking device and optical communication system 失效
公开(公告)号：US06782202B2
公开(公告)日：2004-08-24
申请号：US09865584
申请日：2001-05-29
申请人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
发明人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
IPC分类号： H04B1020
CPC分类号： H04B10/271 , G06F13/4022 , H04B10/27 , H04B10/278
摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

8. 发明授权

US06631447B1 Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed 失效
标题翻译：具有用于控制必须保证高速缓存一致性的处理器数量的控制器的多处理器系统
公开(公告)号：US06631447B1
公开(公告)日：2003-10-07
申请号：US08824411
申请日：1997-03-26
申请人： Michio Morioka , Kenichi Kurosawa , Tetsuaki Nakamikawa , Sakoh Ishikawa
发明人： Michio Morioka , Kenichi Kurosawa , Tetsuaki Nakamikawa , Sakoh Ishikawa
IPC分类号： G06F1208
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0826 , G06F12/1027 , G06F2212/2542
摘要： To provide a large scale multiprocessor system capable of executing an area limited cache coherency control implementing a high speed operation while substantially reducing the amount of processor-to-processor communications there is provided a translation lookaside buffer which retains cache coherency attribute information defining a limitable cache coherent area to maintain data consistency among caches, and a processor memory interface unit includes a cache coherency control which identifies whether cache coherency is required only within a particular cluster of processors or is required for every one of the cache memories in every one of the clusters throughout the system, on the basis of the contents of the cache coherency attribute information. Further, in another version of large scale multiprocessor system, each cluster may be provided with an export directory which registers an identifier of data whose copy is cached in cache memories in other clusters. Thereby, latency in cache coherency procedures can be reduced greatly, since a cache coherent area can be limited in dependence on various characteristics of data. Further, it is also possible to greatly reduce inter-cluster communication quantities, since it is no longer necessary to broadcast to all processors in the system upon every occasion of a memory read/write.
摘要翻译：为了提供能够执行高速操作的区域限制的高速缓存一致性控制的大规模多处理器系统，同时基本上减少了处理器到处理器通信的数量，提供了一种翻译后备缓冲器，其保存定义可限制的高速缓存的高速缓存一致性属性信息相干区域以保持高速缓存之间的数据一致性，并且处理器存储器接口单元包括高速缓存一致性控制，其识别高速缓存一致性是仅在特定的处理器群集中是否需要，或者是每个群集中的每一个高速缓冲存储器都需要在整个系统中，基于缓存一致性属性信息的内容。此外，在大规模多处理器系统的另一版本中，每个集群可以被提供有导出目录，其将其副本的高速缓冲存储器中的数据的标识符注册到其他集群中。因此，可以大大降低高速缓存一致性过程中的等待时间，因为可以根据数据的各种特性来限制高速缓存相干区域。此外，由于在存储器读/写的每个场合不再需要向系统中的所有处理器广播，因此也可以大大减少群间间通信量。

9. 发明授权

US08422830B2 Image processing system with an address snooping apparatus 失效
标题翻译：具有地址窥探设备的图像处理系统
公开(公告)号：US08422830B2
公开(公告)日：2013-04-16
申请号：US11971942
申请日：2008-01-10
申请人： Tetsuaki Nakamikawa , Shoji Muramatsu
发明人： Tetsuaki Nakamikawa , Shoji Muramatsu
IPC分类号： G06K9/54 , G06F21/00 , G06F15/00
CPC分类号： G06T1/20
摘要： An image processing system includes a first image processor that reads out a first image written in a main memory to apply a first process to the first image and write in the main memory as a second image, a second image processor that reads out a second image written in the main memory to apply a second process to the second image and write in the main memory as a second image, and an address snooping apparatus that snoops an address of the image written in the main memory to start the first process when the address is indicated to a previously set first value and start the second process when the address is indicated to a previously set second value, effectively enabling synchronization between a process by a CPU or a special purpose processor and a data delivery/receipt process between pipeline stages.
摘要翻译：一种图像处理系统包括：第一图像处理器，其读出写入主存储器中的第一图像以对第一图像应用第一处理，并将第二图像写入主存储器;第二图像处理器，读出第二图像写入主存储器中以对第二图像应用第二处理并将其写入主存储器中作为第二图像，以及地址窥探装置，其在所述主存储器中写入写入的图像的地址开始第一处理，当地址被指示为先前设置的第一值并且当地址被指示为先前设置的第二值时开始第二处理，有效地实现CPU或专用处理器的处理与流水线级之间的数据传送/接收处理之间的同步。

10. 发明授权

US07272665B2 Modular computer system and I/O module 有权
标题翻译：模块化计算机系统和I / O模块
公开(公告)号：US07272665B2
公开(公告)日：2007-09-18
申请号：US10759193
申请日：2004-01-20
申请人： Tsutomu Yamada , Tetsuaki Nakamikawa , Hiromichi Endoh , Noritaka Matsumoto , Hirokazu Kasashima
发明人： Tsutomu Yamada , Tetsuaki Nakamikawa , Hiromichi Endoh , Noritaka Matsumoto , Hirokazu Kasashima
IPC分类号： G06F3/00 , G06F13/42 , H02J13/00
CPC分类号： G06F13/4095
摘要： Without being restrained to a specific bus scheme, kinds of I/O modules connected to a processing module can be discriminated. Module exclusive selection parts respectively provided in I/O modules connected in a stacked form to a processing module via connectors judge only a module select signal input from terminals in the same position on processing module side connectors to be active. Based thereon, identification information of its own I/O module is output to a predetermined terminal on the connector. Without being restrained to a specific bus scheme, therefore, the processing module can acquire identification information of the I/O modules from a predetermined terminal on a connector. One I/O module can be selected by a simple module selection circuit scheme of inputting module select signals successively output from the processing module to terminals in the same position on processing module side connectors according to the connection order of the I/O modules.
摘要翻译：不受特定总线方案的约束，可以区分连接到处理模块的各种I / O模块。分别在I / O模块中以堆叠形式连接到处理模块的模块专用选择部件通过连接器判断只有模块选择信号从位于处理模块侧连接器上相同位置的端子输入才能激活。基于此，其自身的I / O模块的识别信息被输出到连接器上的预定端子。因此，不受特定总线方案的约束，处理模块可以从连接器上的预定端子获取I / O模块的识别信息。可以通过简单的模块选择电路方案来选择一个I / O模块，该模块选择电路根据I / O模块的连接顺序将从处理模块连续输出的模块选择信号输入到位于处理模块侧连接器上相同位置的端子。

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