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1. 发明申请

US20100188878A1 SEMICONDUCTOR DEVICE THAT SUPRESSES MALFUNCTIONS DUE TO VOLTAGE REDUCTION 审中-公开
标题翻译：减少电压降低故障的半导体器件
公开(公告)号：US20100188878A1
公开(公告)日：2010-07-29
申请号：US12693246
申请日：2010-01-25
申请人： Hiromasa TAKEDA , Kyoichi NAGATA , Satoshi ISA , Mitsuaki KATAGIRI
发明人： Hiromasa TAKEDA , Kyoichi NAGATA , Satoshi ISA , Mitsuaki KATAGIRI
IPC分类号： G11C5/06 , G11C5/14 , G11C7/00
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4091 , G11C2207/105
摘要： A semiconductor device includes a first pad that supplies power to sense amplifiers, a second pad that supplies power to a first circuit connected to the sense amplifiers, a third pad that receives a signal input or outputs a signal at a frequency equal to or higher than a first frequency, and a fourth pad that receives a signal input or outputs a signal at a second frequency lower than the first frequency. The first pad is arranged between and adjacent to the second pads respectively, or arranged between and adjacent to the second and fourth pads respectively. Additionally, the first pad is arranged between the third pads, which are respectively arranged on both sides of the first pad, to be adjacent to the second pad so as to hold the second pad or to be adjacent to the fourth pad so as to hold the fourth pad.
摘要翻译：半导体器件包括向读出放大器供电的第一焊盘，向连接到读出放大器的第一电路供电的第二焊盘;接收信号输入或输出等于或高于第一频率和第四垫，其接收输入或输出低于第一频率的第二频率的信号的信号。第一焊盘分别布置在第二焊盘之间并与之相邻，或者分别布置在第二焊盘之间并且与第二焊盘相邻。此外，第一焊盘被布置在第三焊盘之间，第三焊盘分别布置在第一焊盘的两侧，以与第二焊盘相邻，以便保持第二焊盘或与第四焊盘相邻以便保持第四垫。

2. 发明申请

US20110180934A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110180934A1
公开(公告)日：2011-07-28
申请号：US13014235
申请日：2011-01-26
申请人： Hiromasa TAKEDA , Satoshi ISA , Mitsuaki KATAGIRI
发明人： Hiromasa TAKEDA , Satoshi ISA , Mitsuaki KATAGIRI
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L21/6835 , H01L23/13 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2221/68331 , H01L2224/05554 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48465 , H01L2224/4911 , H01L2224/49113 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.
摘要翻译：半导体器件可以包括：经由间隙彼此分离的第一和第二布线板; 半导体芯片; 第一组和第二组电极垫; 以及第一组和第二组连接垫。半导体芯片固定在第一和第二布线板的上表面上，并且具有与间隙相邻的第一部分。第一和第二组电极焊盘设置在第一部分上。第一和第二组电极焊盘分别与第一和第二布线板的侧表面相对准。第一和第二布线板的侧表面彼此面对。第一和第二组连接焊盘分别设置在第一和第二布线板的下表面上。第一和第二组连接焊盘分别与第一和第二布线板的侧表面相对准。

3. 发明申请

US20130114223A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130114223A1
公开(公告)日：2013-05-09
申请号：US13463317
申请日：2012-05-03
申请人： Satoshi ITAYA , Satoshi ISA , Mitsuaki KATAGIRI , Dai SASAKI
发明人： Satoshi ITAYA , Satoshi ISA , Mitsuaki KATAGIRI , Dai SASAKI
IPC分类号： H05K1/18
CPC分类号： H05K1/181 , G11C5/063 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/0102 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.
摘要翻译：在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

4. 发明申请

US20100193933A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20100193933A1
公开(公告)日：2010-08-05
申请号：US12687311
申请日：2010-01-14
申请人： Yu HASEGAWA , Mitsuaki KATAGIRI , Satoshi ISA , Ken IWAKURA , Dai SASAKI
发明人： Yu HASEGAWA , Mitsuaki KATAGIRI , Satoshi ISA , Ken IWAKURA , Dai SASAKI
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/49171 , H01L2224/73265 , H01L2224/85007 , H01L2224/85051 , H01L2224/85444 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20755 , H01L2924/30105 , H01L2924/00 , H01L2224/48132 , H01L2924/00012 , H01L2924/20757 , H01L2924/2075 , H01L2924/20754 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.
摘要翻译：在本发明的半导体器件中，第二半导体芯片堆叠在其中心区域具有多个接合焊盘的第一半导体芯片上，其间插入有接合层。通过穿过第一和第二半导体芯片之间的空间，分别连接到第一半导体芯片的多个接合焊盘的多条引线在第一半导体芯片的外围边缘被引出到外部。在第一半导体芯片上的区域中设置用于保持多条电线的至少一个子集的保持构件，该区域包括通过使用不同于接合层的材料，在接合焊盘与第一半导体芯片的周边边缘之间的中间点使得电线的子集通常位于第一半导体芯片和第二半导体芯片之间的间隔的中心。

5. 发明申请

US20080072194A1 METHOD FOR DESIGNING DEVICE, SYSTEM FOR AIDING TO DESIGN DEVICE, AND COMPUTER PROGRAM PRODUCT THEREFOR 失效
标题翻译：用于设计设备的方法，用于设计设备的系统，以及计算机程序产品
公开(公告)号：US20080072194A1
公开(公告)日：2008-03-20
申请号：US11854591
申请日：2007-09-13
申请人： Mitsuaki KATAGIRI , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
发明人： Mitsuaki KATAGIRI , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。第二半导体芯片包括耦合到输入焊盘的输出焊盘。调整对象被连接到第一和第二半导体芯片。主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

6. 发明申请

US20080224311A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080224311A1
公开(公告)日：2008-09-18
申请号：US12126681
申请日：2008-05-23
申请人： Satoshi ISA , Mitsuaki KATAGIRI , Fumiyuki OSANAI
发明人： Satoshi ISA , Mitsuaki KATAGIRI , Fumiyuki OSANAI
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译：公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感的半导体芯片。焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

7. 发明申请

US20100208443A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100208443A1
公开(公告)日：2010-08-19
申请号：US12707996
申请日：2010-02-18
申请人： Satoshi ITAYA , Satoshi ISA , Mitsuaki KATAGIRI , Dai SASAKI
发明人： Satoshi ITAYA , Satoshi ISA , Mitsuaki KATAGIRI , Dai SASAKI
IPC分类号： H05K7/00
CPC分类号： H05K1/181 , G11C5/063 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/0102 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.
摘要翻译：在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

8. 发明申请

US20120119387A1 SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE 有权
标题翻译：具有减少环路电感的连接线的半导体封装
公开(公告)号：US20120119387A1
公开(公告)日：2012-05-17
申请号：US13291740
申请日：2011-11-08
申请人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
发明人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
IPC分类号： H01L23/50 , H01L23/522
CPC分类号： H01L23/498 , G11C5/06 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2223/6611 , H01L2224/04042 , H01L2224/05013 , H01L2224/05553 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48463 , H01L2224/49175 , H01L2224/49176 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/15173 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
摘要翻译：半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指，以及多个第二电源电压接合指。信号焊盘通过第一线分别连接到信号键指。第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

9. 发明申请

US20090184409A1 SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS WITH DIFFERENT THICKNESS 有权
标题翻译：半导体器件，包括具有不同厚度的半导体器件
公开(公告)号：US20090184409A1
公开(公告)日：2009-07-23
申请号：US12357895
申请日：2009-01-22
申请人： Mitsuaki KATAGIRI , Hisashi Tanie , Jun Kayamori , Dai Sasaki , Hiroshi Moriya
发明人： Mitsuaki KATAGIRI , Hisashi Tanie , Jun Kayamori , Dai Sasaki , Hiroshi Moriya
IPC分类号： H01L23/02 , H01L25/10 , H01L23/48 , H01L23/485
CPC分类号： H01L25/105 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/50 , H01L24/86 , H01L25/0657 , H01L2224/29101 , H01L2224/29191 , H01L2225/0652 , H01L2225/06555 , H01L2225/06579 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/15331 , H01L2924/30105 , H01L2924/3511 , H01L2924/00
摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
摘要翻译：在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

10. 发明申请

US20120302007A1 SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS WITH DIFFERENT THICKNESS 有权
标题翻译：半导体器件，包括具有不同厚度的半导体器件
公开(公告)号：US20120302007A1
公开(公告)日：2012-11-29
申请号：US13538654
申请日：2012-06-29
申请人： Mitsuaki KATAGIRI , Hisashi TANIE , Jun KAYAMORI , Dai SASAKI , Hiroshi MORIYA
发明人： Mitsuaki KATAGIRI , Hisashi TANIE , Jun KAYAMORI , Dai SASAKI , Hiroshi MORIYA
IPC分类号： H01L21/60
CPC分类号： H01L25/105 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/50 , H01L24/86 , H01L25/0657 , H01L2224/29101 , H01L2224/29191 , H01L2225/0652 , H01L2225/06555 , H01L2225/06579 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/15331 , H01L2924/30105 , H01L2924/3511 , H01L2924/00
摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
摘要翻译：在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

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