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1. 发明申请

US20140119143A1 SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM 有权
标题翻译：半导体器件及其控制方法及数据处理系统
公开(公告)号：US20140119143A1
公开(公告)日：2014-05-01
申请号：US14147692
申请日：2014-01-06
申请人： Kyoichi NAGATA
发明人： Kyoichi NAGATA
IPC分类号： G11C29/04
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
摘要翻译：本文公开了一种半导体器件，其包括全局位线，耦合到正常存储器单元的第一本地位线，耦合到冗余存储器单元的第二局部位线和第二分层开关，对全局位线预充电的预充电电路，冗余确定所访问的地址是否匹配缺陷地址的确定电路以及控制电路。在待机状态下，全局位线和第二局部位线通过第二分层开关进行预充电。在激活状态下，第一本地位线通过第一分层交换机预先充电，随后当冗余确定电路确定地址不匹配时，第二分层交换机被停用以访问正常存储器单元，并且当冗余确定电路确定地址彼此匹配，第一分层交换机被停用以访问冗余存储器单元。

2. 发明申请

US20100085824A1 Semiconductor device having delay control circuit 有权
标题翻译：具有延迟控制电路的半导体装置
公开(公告)号：US20100085824A1
公开(公告)日：2010-04-08
申请号：US12588200
申请日：2009-10-07
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C7/00 , H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.
摘要翻译：具有彼此不同的工作条件的第一延迟电路和第二延迟电路，检测电路，其检测同时输入到第一和第二延迟电路的脉冲信号的传播速度差，以及产生提供了基于来自检测电路的检测结果的选择信号。选择信号被提供给延迟控制电路，该延迟控制电路通过延迟由选择信号控制延迟量的参考信号来产生操作定时信号。通过这种布置，考虑到PVT变化，可以消除设计具有大设计余量的延迟控制电路的延迟量的必要性，结果，可以防止性能下降。

3. 发明授权

US07663411B2 Semiconductor device with a logic circuit 失效
标题翻译：具有逻辑电路的半导体器件
公开(公告)号：US07663411B2
公开(公告)日：2010-02-16
申请号：US12213239
申请日：2008-06-17
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03B21/00
CPC分类号： H03K19/0016
摘要： The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.
摘要翻译：本发明的逻辑门具有包括第一晶体管，第二晶体管和连接切换单元的结构。第一晶体管在其源极处接收第一电压，在其栅极处接收第一输入信号，并从其漏极提供第一输出信号。第二晶体管接收低于其源极处的第一电压的第二电压，在其栅极处接收第二输入信号，并从其漏极提供第二输出信号。连接切换单元连接在第一晶体管的漏极和第二晶体管之间，用于连接和切断第一晶体管和第二晶体管。

4. 发明授权

US07394297B2 Logic gate with reduced sub-threshold leak current 失效
标题翻译：具有降低的亚阈值泄漏电流的逻辑门
公开(公告)号：US07394297B2
公开(公告)日：2008-07-01
申请号：US11399334
申请日：2006-04-07
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03B21/00
CPC分类号： H03K19/0016
摘要： The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.
摘要翻译：本发明的逻辑门具有包括第一晶体管，第二晶体管和连接切换单元的结构。第一晶体管在其源极处接收第一电压，在其栅极处接收第一输入信号，并从其漏极提供第一输出信号。第二晶体管接收低于其源极处的第一电压的第二电压，在其栅极处接收第二输入信号，并从其漏极提供第二输出信号。连接切换单元连接在第一晶体管的漏极和用于连接和切断第一晶体管和第二晶体管的第二晶体管之间。

5. 发明申请

US20050212557A1 Level-conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US20050212557A1
公开(公告)日：2005-09-29
申请号：US11087688
申请日：2005-03-24
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03K17/16 , H03K17/687 , H03K19/00 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0013
摘要： An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.
摘要翻译：将独立的控制信号发送到驱动器控制单元和输出晶体管中的每一个，以防止驱动器控制单元和输出晶体管同时工作并减少直流电流。由于可以容易地选择晶体管比例，所以设计灵活性的程度增加并且实现了速度提高。

6. 发明授权

US06661270B2 Data latch circuit and driving method thereof 有权
标题翻译：数据锁存电路及其驱动方法
公开(公告)号：US06661270B2
公开(公告)日：2003-12-09
申请号：US09738454
申请日：2000-12-15
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03K3289
CPC分类号： H03K3/0372
摘要： A data latch circuit of the present invention, which corresponds to the semiconductor circuit, is provided with a master flip-flop and a slave flip-flop. The master flip-flop fetches a first signal in response to a first clock signal, holds first data corresponding to the first signal as binary data in response to the first clock signal, and also outputs the first data as a second signal. The slave flip-flop fetches the second signal in response to an OR-gated result obtained between the first clock signal and either one or a plurality of second clock signals, and the slave flip-flop holds second data corresponding to the second signal in response to the OR-gated result, and also the slave flip-flop outputs a third signal corresponding to the second data.
摘要翻译：对应于半导体电路的本发明的数据锁存电路设置有主触发器和从触发器。主触发器响应于第一时钟信号获取第一信号，响应于第一时钟信号将对应于第一信号的第一数据保存为二进制数据，并且还将第一数据作为第二信号输出。从触发器响应于在第一时钟信号和一个或多个第二时钟信号之间获得的OR门控结果来取得第二信号，并且从触发器保持对应于第二信号的第二数据作为响应到门控结果，并且从触发器输出对应于第二数据的第三信号。

7. 发明授权

US6009020A Semiconductor memory device having dynamic data amplifier circuit capable of reducing power dissipation 失效
标题翻译：具有能够降低功耗的动态数据放大电路的半导体存储器件
公开(公告)号：US6009020A
公开(公告)日：1999-12-28
申请号：US266731
申请日：1999-03-12
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C11/417 , G11C7/10 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051
摘要： In a semiconductor memory device including a pair of data input/output lines, a data amplifier circuit amplifies voltages at the data input/output lines, and a data maintaining circuit maintains output signals of the data amplifier circuit. A data determination circuit, generates a data determination signal after the data maintaining circuit manintains the output signals of the data amplifier circuit and transmits the data transmitting the data determination signal to the data amplifier circuit, thus suspending the operation of the data amplifier circuit.
摘要翻译：在包括一对数据输入/输出线的半导体存储器件中，数据放大器电路放大数据输入/输出线上的电压，数据保持电路维持数据放大器电路的输出信号。数据确定电路，在数据维持电路之后产生数据确定信号，使数据放大器电路的输出信号变为虚线，并将发送数据确定信号的数据发送到数据放大器电路，从而暂停数据放大器电路的操作。

8. 发明授权

US5995432A Semiconductor memory device having N-channel MOS transistor for pulling up PMOS sources of sense amplifiers 有权
标题翻译：具有用于提取读出放大器的PMOS源的N沟道MOS晶体管的半导体存储器件
公开(公告)号：US5995432A
公开(公告)日：1999-11-30
申请号：US127866
申请日：1998-08-03
申请人： Kyoichi Nagata , Satoshi Isa
发明人： Kyoichi Nagata , Satoshi Isa
IPC分类号： G11C11/401 , G11C7/06 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： H01L27/108 , G11C7/065
摘要： In a semiconductor memory device including a plurality of memory cells connected between sub word lines and bit lines, a plurality of sub word line driver columns for driving the sub word lines, and a plurality of sense amplifier columns for sensing voltages at the bit lines, a plurality of sense amplifier control circuits are provided at cross areas between the sub word line driver columns and the sense amplifier columns. A first sense amplifier control circuit is constructed by a CMOS circuit forming an interface between global input/output lines and local input/output lines. A second sense amplifier control circuit is constructed by an N-channel MOS circuit forming a pull down circuit for pulling down NMOS sources of flip-flops of the sense amplifier columns and a first pull up circuit for pulling up PMOS sources of the flip-flops of said sense amplifier columns. A third sense amplifier control circuit is constructed by a P-channel MOS circuit forming a second pull up circuit for pulling up the PMOS sources of the flip-flops of the sense amplifier columns.
摘要翻译：在包括连接在子字线和位线之间的多个存储单元的半导体存储器件中，用于驱动子字线的多个子字线驱动器列和用于感测位线上的电压的多个读出放大器列，在子字线驱动器列和读出放大器列之间的交叉区域设置多个读出放大器控制电路。第一感测放大器控制电路由形成全局输入/输出线与本地输入/输出线之间的接口的CMOS电路构成。第二读出放大器控制电路由形成用于下拉读出放大器列的触发器的NMOS源的下拉电路的N沟道MOS电路和用于提取触发器的PMOS源的第一上拉电路构成的所述读出放大器列。第三读出放大器控制电路由形成用于提取读出放大器列的触发器的PMOS源的第二上拉电路的P沟道MOS电路构成。

9. 发明授权

US5990671A Constant power voltage generator with current mirror amplifier optimized by level shifters 失效
标题翻译：恒电源电压发生器，电流镜放大器由电平转换器优化
公开(公告)号：US5990671A
公开(公告)日：1999-11-23
申请号：US129408
申请日：1998-08-05
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C11/407 , G05F1/46 , G05F1/56 , G05F3/26 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , G05F3/16
CPC分类号： G05F3/262 , G05F1/465
摘要： A constant power voltage generator produces an internal power voltage from an external power voltage, and includes a current mirror amplifier for producing a control signal representative of the magnitude of potential difference between a first input node and a second input node, a reference voltage generator for producing a reference voltage, a first level shifter for supplying a step-down reference voltage to the first input node and a second level shifter for supplying a step-down power voltage to the second input node, wherein each of the first and second level shifters is implemented by a series combination of field effect transistors so as to easily optimize the potential levels at the first and second input nodes by changing the channel resistance of the field effect transistors.
摘要翻译：恒定电源电压发生器从外部电源电压产生内部电源电压，并且包括用于产生表示第一输入节点和第二输入节点之间的电位差大小的控制信号的电流镜放大器，用于产生参考电压，用于向第一输入节点提供降压参考电压的第一电平移位器和用于向第二输入节点提供降压电源电压的第二电平转换器，其中第一和第二电平转换器通过场效应晶体管的串联组合实现，以便通过改变场效应晶体管的沟道电阻容易地优化第一和第二输入节点处的电位电平。

10. 发明授权

US5841708A Semiconductor memory device having small chip size and redundancy access time 失效
标题翻译：具有小芯片尺寸和冗余访问时间的半导体存储器件
公开(公告)号：US5841708A
公开(公告)日：1998-11-24
申请号：US731742
申请日：1996-10-18
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H01L21/82 , G11C11/401 , G11C29/00 , G11C29/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/80 , G11C29/84
摘要： A semiconductor memory circuit designed so as to prevent delay in redundancy access and increase in the chip area due to lengthy wiring between the redundancy control circuit (the redundancy fuse circuits) and the redundancy cell arrays. Redundancy cell arrays 30-32 are placed in a plurality of memory cell arrays 20-23, and the corresponding redundancy fuse circuits 80-82 disposed to make a line with the redundancy word drivers 51-53, respectively. For example, when a defective address is selected 4n redundancy fuse circuit 80, a redundancy judgment signal RDN suspends all the sense amplifier controllers 40, 43 and 44. A redundancy control information RED1 instructs to select a redundancy word driver 51 and the sense amplifier controllers 41 and 42, to select the redundancy cell array 30.
摘要翻译：一种半导体存储器电路，其设计为防止冗余控制电路（冗余熔丝电路）和冗余单元阵列之间冗长的布线导致的冗余访问延迟和芯片面积的增加。冗余单元阵列30-32被放置在多个存储单元阵列20-23中，并且相应的冗余熔丝电路80-82分别设置成与冗余字驱动器511-53分线。例如，当在4n冗余熔丝电路80中选择有缺陷地址时，冗余判断信号RDN挂起所有读出放大器控制器40,43和44.冗余控制信息RED1指示选择冗余字驱动器51和读出放大器控制器如图41和图42所示，选择冗余单元阵列30。

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