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1. 发明授权

US08804395B2 Semiconductor device, control method thereof and data processing system 有权
公开(公告)号：US08804395B2
公开(公告)日：2014-08-12
申请号：US14147692
申请日：2014-01-06
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C5/06 , G11C29/00 , G11C5/02
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

2. 发明授权

US08670284B2 Semiconductor device, control method thereof and data processing system 失效
标题翻译：半导体器件，其控制方法和数据处理系统
公开(公告)号：US08670284B2
公开(公告)日：2014-03-11
申请号：US13431654
申请日：2012-03-27
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C7/00
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
摘要翻译：本文公开了一种半导体器件，其包括全局位线，耦合到正常存储器单元的第一本地位线，耦合到冗余存储器单元的第二局部位线和第二分层开关，对全局位线预充电的预充电电路，冗余确定所访问的地址是否匹配缺陷地址的确定电路以及控制电路。在待机状态下，全局位线和第二局部位线通过第二分层开关进行预充电。在激活状态下，第一本地位线通过第一分层交换机预先充电，随后当冗余确定电路确定地址不匹配时，第二分层交换机被停用以访问正常存储器单元，并且当冗余确定电路确定地址彼此匹配，第一分层交换机被停用以访问冗余存储器单元。

3. 发明申请

US20120250437A1 SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM 失效
标题翻译：半导体器件及其控制方法及数据处理系统
公开(公告)号：US20120250437A1
公开(公告)日：2012-10-04
申请号：US13431654
申请日：2012-03-27
申请人： Kyoichi NAGATA
发明人： Kyoichi NAGATA
IPC分类号： G11C29/04
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
摘要翻译：本文公开了一种半导体器件，其包括全局位线，耦合到正常存储器单元的第一本地位线，耦合到冗余存储器单元的第二局部位线和第二分层开关，对全局位线预充电的预充电电路，冗余确定所访问的地址是否匹配缺陷地址的确定电路以及控制电路。在待机状态下，全局位线和第二局部位线通过第二分层开关进行预充电。在激活状态下，第一本地位线通过第一分层交换机预先充电，随后当冗余确定电路确定地址不匹配时，第二分层交换机被停用以访问正常存储器单元，并且当冗余确定电路确定地址彼此匹配，第一分层交换机被停用以访问冗余存储器单元。

4. 发明授权

US08208324B2 Semiconductor memory device that can relief defective address 有权
标题翻译：可以缓解缺陷地址的半导体存储器件
公开(公告)号：US08208324B2
公开(公告)日：2012-06-26
申请号：US12654202
申请日：2009-12-14
申请人： Noriaki Mochida , Kyoichi Nagata
发明人： Noriaki Mochida , Kyoichi Nagata
IPC分类号： G11C29/00 , G11C7/06 , G11C8/00
CPC分类号： G11C11/4076 , G11C11/4091 , G11C29/84
摘要： To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.
摘要翻译：为了构成存储单元阵列，设置在存储单元阵列的外部并放大从存储单元阵列读出的数据的读取放大器，设置在存储单元阵列外部的写放大器，并放大要写入存储单元阵列的数据以及设置在存储单元阵列外部并经由开关连接到读取放大器的输入端子和写入放大器的输出端子的释放存储单元。利用这种配置，根据存储块的位置，不需要改变操作主放大器和浮雕存储单元的定时。此外，可以使连接到浮雕存储单元所需的部件的数量最小化。

5. 发明申请

US20080258774A1 Semiconductor device with a logic circuit 失效
标题翻译：具有逻辑电路的半导体器件
公开(公告)号：US20080258774A1
公开(公告)日：2008-10-23
申请号：US12213239
申请日：2008-06-17
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03K19/20
CPC分类号： H03K19/0016
摘要： The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.
摘要翻译：本发明的逻辑门具有包括第一晶体管，第二晶体管和连接切换单元的结构。第一晶体管在其源极处接收第一电压，在其栅极处接收第一输入信号，并从其漏极提供第一输出信号。第二晶体管接收低于其源极处的第一电压的第二电压，在其栅极处接收第二输入信号，并从其漏极提供第二输出信号。连接切换单元连接在第一晶体管的漏极和第二晶体管之间，用于连接和切断第一晶体管和第二晶体管。

6. 发明授权

US07288963B2 Level-conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US07288963B2
公开(公告)日：2007-10-30
申请号：US11087688
申请日：2005-03-24
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.
摘要翻译：将独立的控制信号发送到驱动器控制单元和输出晶体管中的每一个，以防止驱动器控制单元和输出晶体管同时工作并减少直流电流。由于可以容易地选择晶体管比例，所以设计灵活性的程度增加并且实现了速度提高。

7. 发明授权

US06178139B1 Semiconductor memory device comprised of a double data rate-synchronous dynamic random access memory 有权
标题翻译：半导体存储器件由双数据速率同步动态随机存取存储器构成
公开(公告)号：US06178139B1
公开(公告)日：2001-01-23
申请号：US09427955
申请日：1999-10-27
申请人： Atsunori Hirobe , Kyoichi Nagata
发明人： Atsunori Hirobe , Kyoichi Nagata
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C8/18 , G11C11/4076
摘要： A semiconductor memory device which enables holding of two or more addresses and selecting of an address output corresponding to kinds of commands with a sufficient operational margin. The semiconductor memory device of the present invention is so configured that a command decoder generates a first controlling signal after a first period following the inputting of a read command, a second controlling signal after a second period following the inputting of a write command, and an operation instructing signal to be fed to a column control circuit in response to first and second controlling signals, and a burst counter makes an input address delayed by first and second periods and outputs the address delayed by the first period as a read address in response to a first controlling signal and the address delayed by the second period as a write address in response to a second controlling signal.
摘要翻译：一种半导体存储器件，其能够保持两个或更多个地址，并且以足够的操作余量选择与命令种类相对应的地址输出。本发明的半导体存储器件被配置为使得命令解码器在输入读命令之后的第一周期之后产生第一控制信号，在输入写命令之后的第二周期之后产生第二控制信号，以及操作指令信号响应于第一和第二控制信号被馈送到列控制电路，并且突发计数器使输入地址被延迟第一和第二周期，并且响应于第一控制信号和响应于第二控制信号延迟到第二周期的地址作为写入地址。

8. 发明授权

US6061281A Redundancy method and semiconductor circuit 失效
标题翻译：冗余方法和半导体电路
公开(公告)号：US6061281A
公开(公告)日：2000-05-09
申请号：US193358
申请日：1998-11-17
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： In a redundancy method, a redundancy switch is shared by a plurality of redundancy objects. The redundancy switch is divisionally, independently connected to recovery lines in the redundancy objects by a plurality of redundancies in the redundancy switch. Defects generated in the redundancy objects are replaced with information of the recovery lines in the redundancy objects that are connected to the redundancy switch, thereby recovering the defects. A semiconductor circuit for the above method is also disclosed.
摘要翻译：在冗余方法中，冗余切换由多个冗余对象共享。冗余开关通过冗余开关中的多个冗余分开独立地连接到冗余对象中的恢复线。在冗余对象中生成的缺陷被替换为连接到冗余交换机的冗余对象中的恢复行的信息，从而恢复缺陷。还公开了用于上述方法的半导体电路。

9. 发明授权

US5986966A Semiconductor memory device capable of effectively resetting sub word lines 失效
标题翻译：能够有效地复位子字线的半导体存储器件
公开(公告)号：US5986966A
公开(公告)日：1999-11-16
申请号：US55956
申请日：1998-04-07
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C11/407 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/408 , G11C7/00
CPC分类号： G11C8/14 , G11C11/408 , G11C11/4085 , G11C8/08
摘要： In a semiconductor memory device, a plurality of main word lines a plurality of pairs of first and second sub word lines, a plurality of first sub word line drive circuits and a plurality of second sub word line drive circuits are provided. Each of the first word line drive circuits is connected to one of the main word lines and at least two pairs of the pairs of first and second sub word lines for activating and deactivating one of the first sub word lines and deactivating the second sub word lines. Each of the second sub word line drive circuits is connected to one of the main word lines and at least two pairs of the pairs of first and second sub word lines for activating and deactivating one of the second sub word lines and deactivating the first sun word lines.
摘要翻译：在半导体存储器件中，提供多个主字线，多对第一和第二子字线，多个第一子字线驱动电路和多个第二子字线驱动电路。第一字线驱动电路中的每一个连接到主字线之一和至少两对第一和第二子字线对，用于激活和去激活第一子字线中的一个并且去激活第二子字线。第二子字线驱动电路中的每一个连接到一个主字线和至少两对第一和第二子字线对，用于激活和去激活第二子字线中的一个并且去激活第一太阳字线条。

10. 发明申请

US20140119143A1 SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM 有权
标题翻译：半导体器件及其控制方法及数据处理系统
公开(公告)号：US20140119143A1
公开(公告)日：2014-05-01
申请号：US14147692
申请日：2014-01-06
申请人： Kyoichi NAGATA
发明人： Kyoichi NAGATA
IPC分类号： G11C29/04
CPC分类号： G11C29/84 , G11C5/025 , G11C7/18 , G11C11/4094 , G11C29/04 , G11C29/785 , G11C29/80 , G11C29/81 , G11C29/848
摘要： Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
摘要翻译：本文公开了一种半导体器件，其包括全局位线，耦合到正常存储器单元的第一本地位线，耦合到冗余存储器单元的第二局部位线和第二分层开关，对全局位线预充电的预充电电路，冗余确定所访问的地址是否匹配缺陷地址的确定电路以及控制电路。在待机状态下，全局位线和第二局部位线通过第二分层开关进行预充电。在激活状态下，第一本地位线通过第一分层交换机预先充电，随后当冗余确定电路确定地址不匹配时，第二分层交换机被停用以访问正常存储器单元，并且当冗余确定电路确定地址彼此匹配，第一分层交换机被停用以访问冗余存储器单元。

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