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1. 发明授权

US08680881B2 Test method and interposer used therefor 失效
标题翻译：用于此的测试方法和插入器
公开(公告)号：US08680881B2
公开(公告)日：2014-03-25
申请号：US13044717
申请日：2011-03-10
申请人： Yutaka Uematsu , Hideki Osaka , Satoshi Nakamura , Satoshi Muraoka , Mitsuaki Katagiri , Ken Iwakura , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Satoshi Nakamura , Satoshi Muraoka , Mitsuaki Katagiri , Ken Iwakura , Yukitoshi Hirose
IPC分类号： G01R31/00
CPC分类号： G01R31/2889
摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.
摘要翻译：安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

2. 发明申请

US20120119387A1 SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE 有权
标题翻译：具有减少环路电感的连接线的半导体封装
公开(公告)号：US20120119387A1
公开(公告)日：2012-05-17
申请号：US13291740
申请日：2011-11-08
申请人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
发明人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
IPC分类号： H01L23/50 , H01L23/522
CPC分类号： H01L23/498 , G11C5/06 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2223/6611 , H01L2224/04042 , H01L2224/05013 , H01L2224/05553 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48463 , H01L2224/49175 , H01L2224/49176 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/15173 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
摘要翻译：半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指，以及多个第二电源电压接合指。信号焊盘通过第一线分别连接到信号键指。第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

3. 发明授权

US08633596B2 Semiconductor package with bonding wires of reduced loop inductance 有权
标题翻译：具有降低环路电感的接合线的半导体封装
公开(公告)号：US08633596B2
公开(公告)日：2014-01-21
申请号：US13291740
申请日：2011-11-08
申请人： Mitsuaki Katagiri , Ken Iwakura , Yutaka Uematsu
发明人： Mitsuaki Katagiri , Ken Iwakura , Yutaka Uematsu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/498 , G11C5/06 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2223/6611 , H01L2224/04042 , H01L2224/05013 , H01L2224/05553 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48463 , H01L2224/49175 , H01L2224/49176 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/15173 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
摘要翻译：半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指，以及多个第二电源电压接合指。信号焊盘通过第一线分别连接到信号键指。第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

4. 发明申请

US20120200159A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120200159A1
公开(公告)日：2012-08-09
申请号：US13366717
申请日：2012-02-06
申请人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
发明人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
IPC分类号： H02J4/00
CPC分类号： H03K19/00361 , G11C7/02 , G11C11/4074 , G11C11/4076 , G11C11/4096 , Y10T307/50
摘要： A semiconductor device includes: first and second power supply wirings VDDQ and VSSQ, respectively; an output circuit 12 arranged between VDDQ and VSSQ; and a noise cancellation circuit 13 arranged between VDDQ and VSSQ. The noise cancellation circuit 13 produces a damped oscillation for the SSN oscillation noise that is generated when a logic level outputted to an output node of the output circuit is switched and that exponentially damps and oscillates at a predetermined period. The damped oscillation produced by the noise cancellation circuit 13 is delayed by half a period of the SSN oscillation noise and has a direction opposite to that of the SSN oscillation noise and hence the damped oscillation and the SSN oscillation noise counteract each other.
摘要翻译：半导体器件分别包括：第一和第二电源配线VDDQ和VSSQ; 布置在VDDQ和VSSQ之间的输出电路12; 以及布置在VDDQ和VSSQ之间的噪声消除电路13。噪声消除电路13产生用于当输出到输出电路的输出节点的逻辑电平被切换并且以预定周期指数衰减和振荡时产生的SSN振荡噪声的阻尼振荡。由噪声消除电路13产生的阻尼振荡被延迟SSN振荡噪声的一半周期，并且具有与SSN振荡噪声相反的方向，因此阻尼振荡和SSN振荡噪声相互抵消。

5. 发明申请

US20140103542A1 SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE 有权
标题翻译：具有减少环路电感的连接线的半导体封装
公开(公告)号：US20140103542A1
公开(公告)日：2014-04-17
申请号：US14109618
申请日：2013-12-17
申请人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
发明人： Mitsuaki KATAGIRI , Ken Iwakura , Yutaka Uematsu
IPC分类号： H01L23/498
CPC分类号： H01L23/498 , G11C5/06 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2223/6611 , H01L2224/04042 , H01L2224/05013 , H01L2224/05553 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48463 , H01L2224/49175 , H01L2224/49176 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/15173 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.
摘要翻译：半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指，以及多个第二电源电压接合指。信号焊盘通过第一线分别连接到信号键指。第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

6. 发明授权

US08581417B2 Semiconductor device stack with bonding layer and wire retaining member 失效
公开(公告)号：US08581417B2
公开(公告)日：2013-11-12
申请号：US12687311
申请日：2010-01-14
申请人： Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
发明人： Yu Hasegawa , Mitsuaki Katagiri , Satoshi Isa , Ken Iwakura , Dai Sasaki
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/49171 , H01L2224/73265 , H01L2224/85007 , H01L2224/85051 , H01L2224/85444 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20755 , H01L2924/30105 , H01L2924/00 , H01L2224/48132 , H01L2924/00012 , H01L2924/20757 , H01L2924/2075 , H01L2924/20754 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

7. 发明申请

US20110084395A1 Semiconductor package substrate and semiconductor device having the same 审中-公开
标题翻译：半导体封装基板和具有该半导体封装基板的半导体器件
公开(公告)号：US20110084395A1
公开(公告)日：2011-04-14
申请号：US12923712
申请日：2010-10-05
申请人： Hiromasa Takeda , Satoshi Isa , Mitsuaki Katagiri , Ken Iwakura , Yu Hasegawa
发明人： Hiromasa Takeda , Satoshi Isa , Mitsuaki Katagiri , Ken Iwakura , Yu Hasegawa
IPC分类号： H01L23/48
CPC分类号： H01L24/50 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality.
摘要翻译：半导体器件包括其上安装半导体芯片的半导体芯片和封装衬底。封装衬底具有连接到半导体芯片的内部端子，连接到内部端子的前表面布线，连接到外部电极的后表面布线以及连接前表面布线和背面布线的触点。在多个接触中，用于信号传输的布线中包括的一些触点设置在内部端子附近。因此，从半导体芯片引出的信号立即从封装基板的芯片安装表面取走。这降低了封装衬底和芯片之间的布线之间的浮动电容，从而提高了信号质量。

8. 发明申请

US20090327981A1 Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged 审中-公开
标题翻译：半导体器件或印刷线路板设计方法和设计支持系统，通过使用表示在封装时发生的寄生元件的半导体器件模型来实现设置
公开(公告)号：US20090327981A1
公开(公告)日：2009-12-31
申请号：US12457930
申请日：2009-06-25
申请人： Satoshi Nakamura , Tsutomu Hara , Mitsuaki Katagiri , Yukitoshi Hirose , Satoshi Itaya , Ken Iwakura
发明人： Satoshi Nakamura , Tsutomu Hara , Mitsuaki Katagiri , Yukitoshi Hirose , Satoshi Itaya , Ken Iwakura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78 , H05K1/181 , H05K3/0005
摘要： Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.
摘要翻译：获取校正电路模型，用于校正在电路板上安装时变化的电特性参数。校正电路模型被添加到单独的模型中，该模型表示隔离的单独的半导体器件以产生表示板安装状态的半导体器件的半导体器件模型。表示调整对象系统的等效电路模型连接到所创建的半导体器件模型，并且基于与等效电路模型相连接的半导体器件模型，与调整对象系统相关的调整对象值为计算。将这些调整对象值与预先确定的限制值进行比较，并且基于比较结果，确定调整对象系统的设计指南。

9. 发明授权

US5424164A Image forming method 失效
标题翻译：图像形成方法
公开(公告)号：US5424164A
公开(公告)日：1995-06-13
申请号：US338832
申请日：1994-11-10
申请人： Masato Satomura , Ken Iwakura , Akira Igarashi
发明人： Masato Satomura , Ken Iwakura , Akira Igarashi
IPC分类号： G03F7/004 , B41M5/26 , B41M5/323 , G03C1/52 , G03C5/18 , G03F7/00 , G03F7/016 , G03C1/72
CPC分类号： G03C1/52 , G03C5/18 , G03F7/002
摘要： A recording material which comprises a support having provided thereon capsules containing a photosensitive diazonium salt, and a polymerizable coupler. The recording material can give a predetermined hue when light, pressure, heat and the like are applied alone or in combination. The main advantages of the recording material are that a specific hue can be selected safely, mixing of colors can be avoided, desensitization problem does not occur and a fixed image can be obtained.
摘要翻译：一种记录材料，其包括其上提供有含有光敏重氮盐的胶囊的支持体和可聚合成色剂。当单独或组合施加光，压力，热等时，记录材料可以给出预定的色调。记录材料的主要优点是可以安全地选择特定的色调，可以避免颜色混合，不会发生脱敏问题，并且可以获得固定的图像。

10. 发明授权

US5260253A Heat-sensitive recording material 失效
公开(公告)号：US5260253A
公开(公告)日：1993-11-09
申请号：US906474
申请日：1992-06-30
申请人： Hiroshi Kawakami , Ken Iwakura
发明人： Hiroshi Kawakami , Ken Iwakura
IPC分类号： B41M5/333 , B41M5/28
CPC分类号： B41M5/3333
摘要： A heat-sensitive recording material comprising a support having thereon a heat-sensitive color forming layer comprising an electron-donating colorless dye and an electron-accepting compound, wherein said electron-accepting compound is a bisthiourea compound.

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