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1. 发明授权

US06049221A Semiconductor integrated circuit system having function of automatically adjusting output resistance value 失效
标题翻译：具有自动调节输出电阻值功能的半导体集成电路系统
公开(公告)号：US06049221A
公开(公告)日：2000-04-11
申请号：US111804
申请日：1998-07-08
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Hideki Murayama , Akira Yamagiwa , Yasuhiro Ishii , Naoki Hamanaka , Masabumi Shibata
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Hideki Murayama , Akira Yamagiwa , Yasuhiro Ishii , Naoki Hamanaka , Masabumi Shibata
IPC分类号： H03K19/003 , H03K19/00 , H03K19/0175 , H04L25/02 , H03K19/175
CPC分类号： H03K19/0005
摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.
摘要翻译：具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

2. 发明授权

US06335867B1 Apparatus for interconnecting logic boards 失效
标题翻译：用于互连逻辑板的装置
公开(公告)号：US06335867B1
公开(公告)日：2002-01-01
申请号：US09708594
申请日：2000-11-09
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
IPC分类号： H05K0114
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K1/14 , H05K7/1445
摘要： Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.
摘要翻译：用于互连逻辑板的装置设置有背板，连接到背板的多个逻辑板，以及连接到背板的多个互连板，用于互连多个逻辑板。在该装置中，多个逻辑板连接到背板，逻辑板与互连板成垂直的垂直位置，并且距离互连板一定距离。

3. 发明授权

US6163464A Apparatus for interconnecting logic boards 失效
公开(公告)号：US6163464A
公开(公告)日：2000-12-19
申请号：US128779
申请日：1998-08-04
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
IPC分类号： G06F3/00 , G06F1/18 , H05K1/14 , H05K7/14
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K1/14 , H05K7/1445
摘要： Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.

4. 发明授权

US5872471A Simultaneous bidirectional transmission circuit 失效
标题翻译：同时双向传输电路
公开(公告)号：US5872471A
公开(公告)日：1999-02-16
申请号：US773307
申请日：1996-12-24
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Toshitsugu Takekuma , Toshiro Takahashi , Tatsuhiro Aida
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Toshitsugu Takekuma , Toshiro Takahashi , Tatsuhiro Aida
IPC分类号： H03K19/0185 , H04L5/14 , H03K17/00
CPC分类号： H03K19/018592 , H04L5/1423
摘要： In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.
摘要翻译：在用于经由传输线在LSI之间进行同时双向通信的同时双向传输电路中，连接到传输线的输入/输出电路被包括在LSI中。输入/输出电路具有驱动器和接收器。驱动器根据LSI内的逻辑信号将输出信号发送到传输线。接收机通过传输线接收具有接收信号和输出信号的混合的混合信号。由LSI中的接收机接收到的信号已被另一方发送到传输线，即与其通信的另一个LSI。接收器也接收逻辑信号输出。接收导出混合信号和逻辑信号输出之间的差异，从而从混合信号中去除逻辑信号的分量，并输出接收信号。接收器具有用于接收逻辑信号并将其输出到偏置电路的参考电路，用于产生与参考电路的内部电阻相分离的电压信号的偏置电路，以及用于接收混合信号和分频的差分接收器电压信号并输出它们之间的差异。参考电路和偏置电路通过使用MOS晶体管形成。

5. 发明授权

US5867541A Method and system for synchronizing data having skew 失效
标题翻译：用于同步具有偏斜的数据的方法和系统
公开(公告)号：US5867541A
公开(公告)日：1999-02-02
申请号：US441613
申请日：1995-05-15
申请人： Akira Tanaka , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
发明人： Akira Tanaka , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
IPC分类号： G06F13/42 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0337 , H04L7/0037 , H04L7/0008
摘要： Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.
摘要翻译：数据从多个发射机中的任何一个与第一时钟同步发送。接收机与第一时钟同步地接收数据，第二时钟与第一时钟具有预定的相位关系。先前在接收机中保持与多个发射机有关的数据接收条件的控制信息，以根据控制信息来控制接收机的接收条件。

6. 发明授权

US5666302A Simultaneous bidirectional transmission apparatus for transmitting and receiving differential signals 失效
标题翻译：用于发送和接收差分信号的同时双向传输装置
公开(公告)号：US5666302A
公开(公告)日：1997-09-09
申请号：US496195
申请日：1995-06-28
申请人： Akira Tanaka , Kenichi Ishibashi , Akira Yamagiwa , Takehisa Hayashi
发明人： Akira Tanaka , Kenichi Ishibashi , Akira Yamagiwa , Takehisa Hayashi
IPC分类号： H04L5/14 , H04B1/58 , H04B3/20 , H04L25/02 , G06G7/02
CPC分类号： H04B1/58 , H04B1/583 , H04B1/586
摘要： A simultaneous bidirectional transmission apparatus for transmitting and receiving differential signals solves a generation of pulse noise problem in the receiving circuit due to the inversion of the output of the transmission circuit. For a pair of input/output devices connected together by transmission lines, each input/output device has a differential transmitting circuit, a differential receiving circuit and six resistors. The output of the transmitting circuit does not affect an input to the receiving circuit, and the receiving circuit receives only the output of the transmitting circuit of the other input/output device. The resistors, a passive element circuit and the output resistance of the transmitting circuit form, in combination, a waveform shaping filter and a matching terminating circuit.
摘要翻译：用于发送和接收差分信号的同时双向传输装置由于传输电路的输出反转而解决接收电路中的脉冲噪声问题的产生。对于通过传输线连接在一起的一对输入/输出设备，每个输入/输出设备具有差分发射电路，差分接收电路和六个电阻器。发送电路的输出不影响到接收电路的输入，接收电路仅接收另一个输入/输出装置的发送电路的输出。电阻器，无源元件电路和发射电路的输出电阻组合形成波形整形滤波器和匹配终端电路。

7. 发明授权

US5621774A Method and apparatus for synchronizing parallel data transfer 失效
标题翻译：用于同步数据传输的方法和装置
公开(公告)号：US5621774A
公开(公告)日：1997-04-15
申请号：US348242
申请日：1994-11-28
申请人： Kenichi Ishibashi , Akira Tanaka , Akira Yamagiwa , Takehisa Hayashi
发明人： Kenichi Ishibashi , Akira Tanaka , Akira Yamagiwa , Takehisa Hayashi
IPC分类号： H04L25/02 , G06F1/10 , H04L7/00 , H04L7/033 , H04L7/04
CPC分类号： G06F1/10 , H04L7/0008 , H04L7/0037 , H04L7/0083 , H04L7/0337
摘要： A data transfer apparatus includes a transmitting apparatus having a pulse generation circuit for generating a plurality of data and a clock having a predetermined timing relation to the plurality of data, a receiving apparatus having latch circuits supplied with the clock and data for latching the plurality of data at a timing of the clock, respectively, transmission lines for connecting the transmitting apparatus and the receiving apparatus, a variable delay circuit for delaying the clock or data to be supplied to the latch circuits, and a variable delay control circuit for controlling an amount of delay of the variable delay circuit by means of output signals of the latch circuits to thereby minimize the cycle time of the data and clock in the data transfer between apparatuses.
摘要翻译：一种数据传送装置，包括具有用于产生多个数据的脉冲发生电路和与该多个数据具有预定定时关系的时钟的发送装置，具有提供有时钟的锁存电路的接收装置和用于锁存多个数据的数据在时钟时刻的数据分别是用于连接发送装置和接收装置的传输线，用于延迟提供给锁存电路的时钟或数据的可变延迟电路，以及用于控制数量的可变延迟控制电路通过锁存电路的输出信号延迟可变延迟电路，从而最小化数据和时钟在设备之间的数据传输中的周期时间。

8. 发明授权

US5087829A High speed clock distribution system 失效
标题翻译：高速时钟分配系统
公开(公告)号：US5087829A
公开(公告)日：1992-02-11
申请号：US443503
申请日：1989-12-01
申请人： Kenichi Ishibashi , Takehisa Hayashi , Toshio Doi , Mitsuo Asai , Noboru Masuda , Akira Yamagiwa , Toshihiro Okabe
发明人： Kenichi Ishibashi , Takehisa Hayashi , Toshio Doi , Mitsuo Asai , Noboru Masuda , Akira Yamagiwa , Toshihiro Okabe
IPC分类号： H03K5/15
CPC分类号： H03K5/15
摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.
摘要翻译：本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号：延迟时间被调整的延迟电路组。时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

9. 发明授权

US5794020A Data transfer apparatus fetching reception data at maximum margin of timing 失效
标题翻译：数据传送装置以最大的定时边缘取出接收数据
公开(公告)号：US5794020A
公开(公告)日：1998-08-11
申请号：US663982
申请日：1996-06-14
申请人： Akira Tanaka , Toshio Doi , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
发明人： Akira Tanaka , Toshio Doi , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
IPC分类号： H04L7/00 , G06F1/12 , H04L7/02 , H04L7/033 , H04L7/08
CPC分类号： H04L7/0337 , H04L7/0008 , H04L7/0041
摘要： A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.
摘要翻译：第一可变延迟电路延迟从输入缓冲器输出的发送单元的接收数据，并将延迟的数据生成到数据未识别时间检测部分。第一和第二锁存器分别在第三锁存器的锁存定时之前和之后以规则的间隔分别具有第二和第三可变延迟电路接收和输出的锁存定时。在调整操作中，第二和第三可变延迟电路的延迟量被固定为足够小于传送周期的值，可变延迟电路的延迟量增加，判断电路检测到接收的前一边缘数据，随后，第二和第三可变延迟电路的延迟量依次增加同时保持相同的值，并且检测接收数据的后沿。在这种情况下，第三锁存器的定时被设置为最大裕量的最佳点。在正常操作中，判断电路检测到与最佳点的偏差，并且根据检测精细地调整第一可变延迟电路的延迟量，从而将接收数据的锁存定时保持在最佳点。

10. 发明授权

US06766404B1 Branch bus system for inter-LSI data transmission 失效
标题翻译：分支总线系统，用于LSI间数据传输
公开(公告)号：US06766404B1
公开(公告)日：2004-07-20
申请号：US09568055
申请日：2000-05-10
申请人： Hideki Osaka , Akira Yamagiwa , Kenichi Ishibashi
发明人： Hideki Osaka , Akira Yamagiwa , Kenichi Ishibashi
IPC分类号： G06F100
CPC分类号： H04L25/0278 , G06F13/4077
摘要： A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.
摘要翻译：快速传输总线系统，能够快速传输数据，在分支点无反射。具有恒定阻抗接口的四个LSI通过两个可变电阻器连接，每个可变电阻器具有三个信号端子。可变阻抗LSI连接在这些可变电阻之间。当连接到可变电阻器的LSI不能用作总线驱动器时，每个可变电阻器中的三个可变电阻元件被设置为连接线的特性阻抗Zo的1/3，并且以Y- 字母形状。当连接到可变电阻器的LSI中的一个作为总线驱动器工作时，可变电阻元件的值被设置为低阻抗或Zo。

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