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1. 发明授权

US07034568B2 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US07034568B2
公开(公告)日：2006-04-25
申请号：US10886035
申请日：2004-07-08
申请人： Hiroki Yamashita , Akio Koyama , Tatsuhiro Aida , Atsushi Itoh , Masahito Sonehara
发明人： Hiroki Yamashita , Akio Koyama , Tatsuhiro Aida , Atsushi Itoh , Masahito Sonehara
IPC分类号： H03K17/16
CPC分类号： H03K19/00369 , H03F1/301 , H03K19/09448
摘要： The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage. The reference-voltage generating circuit 119 comprises an n-type MOS transistor 111, a bipolar transistor 112 which determines the drain voltage of the n-type MOS transistor 111, and a control circuit 120 for controlling the drain current of the n-type MOS transistor 111.
摘要翻译：电流源电流的电源电压依赖性降低，电源电压降低。本发明包括发射极耦合逻辑电路118和参考电压产生电路119，用于产生用于控制恒流电源n型MOS晶体管110的漏极电流（=电流源电流ICS）的参考电压VCSC。发射极耦合逻辑电路118包括由一对发射极耦合双极晶体管106和107构成的电流开关，与电流开关串联连接的恒流供应n型MOS晶体管110和电阻器装置108 和109分别与双极晶体管106和107串联连接以获得输出电压。参考电压产生电路119包括n型MOS晶体管111，确定n型MOS晶体管111的漏极电压的双极晶体管112和用于控制n型MOS晶体管111的漏极电流的控制电路120 晶体管111。

2. 发明授权

US5872471A Simultaneous bidirectional transmission circuit 失效
标题翻译：同时双向传输电路
公开(公告)号：US5872471A
公开(公告)日：1999-02-16
申请号：US773307
申请日：1996-12-24
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Toshitsugu Takekuma , Toshiro Takahashi , Tatsuhiro Aida
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Toshitsugu Takekuma , Toshiro Takahashi , Tatsuhiro Aida
IPC分类号： H03K19/0185 , H04L5/14 , H03K17/00
CPC分类号： H03K19/018592 , H04L5/1423
摘要： In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.
摘要翻译：在用于经由传输线在LSI之间进行同时双向通信的同时双向传输电路中，连接到传输线的输入/输出电路被包括在LSI中。输入/输出电路具有驱动器和接收器。驱动器根据LSI内的逻辑信号将输出信号发送到传输线。接收机通过传输线接收具有接收信号和输出信号的混合的混合信号。由LSI中的接收机接收到的信号已被另一方发送到传输线，即与其通信的另一个LSI。接收器也接收逻辑信号输出。接收导出混合信号和逻辑信号输出之间的差异，从而从混合信号中去除逻辑信号的分量，并输出接收信号。接收器具有用于接收逻辑信号并将其输出到偏置电路的参考电路，用于产生与参考电路的内部电阻相分离的电压信号的偏置电路，以及用于接收混合信号和分频的差分接收器电压信号并输出它们之间的差异。参考电路和偏置电路通过使用MOS晶体管形成。

3. 发明申请

US20050068066A1 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US20050068066A1
公开(公告)日：2005-03-31
申请号：US10886035
申请日：2004-07-08
申请人： Hiroki Yamashita , Akio Koyama , Tatsuhiro Aida , Atsushi Itoh , Masahito Sonehara
发明人： Hiroki Yamashita , Akio Koyama , Tatsuhiro Aida , Atsushi Itoh , Masahito Sonehara
IPC分类号： H03K19/086 , H03F1/30 , H03F3/45 , H03K5/22 , H03K19/003 , H03K19/0944
CPC分类号： H03K19/00369 , H03F1/301 , H03K19/09448
摘要： The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage. The reference-voltage generating circuit 119 comprises an n-type MOS transistor 111, a bipolar transistor 112 which determines the drain voltage of the n-type MOS transistor 111, and a control circuit 120 for controlling the drain current of the n-type MOS transistor 111.
摘要翻译：电流源电流的电源电压依赖性降低，电源电压降低。本发明包括发射极耦合逻辑电路118和参考电压产生电路119，用于产生用于控制恒流电源n型MOS晶体管110的漏极电流（=电流源电流ICS）的参考电压VCSC。发射极耦合逻辑电路118包括由一对发射极耦合双极晶体管106和107构成的电流开关，与电流开关串联连接的恒流供应n型MOS晶体管110和电阻器装置108 和109分别与双极晶体管106和107串联连接以获得输出电压。参考电压产生电路119包括n型MOS晶体管111，确定n型MOS晶体管111的漏极电压的双极晶体管112和用于控制n型MOS晶体管111的漏极电流的控制电路120 晶体管111。

4. 发明申请

US20100271103A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20100271103A1
公开(公告)日：2010-10-28
申请号：US12429172
申请日：2009-04-23
申请人： Nao Miyamoto , Tatsuhiro Aida , Shinobu Yabuki
发明人： Nao Miyamoto , Tatsuhiro Aida , Shinobu Yabuki
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown.
摘要翻译：当高电压输出为Hi时，第一N型晶体管和第二P型晶体管处于截止状态，第二N型晶体管和第一P型晶体管处于导通状态，其中a 对第一N型晶体管的漏源施加高电压。在将高电压输出转换为Lo的过程中，第一N型晶体管的栅极电位曾经被置于VDD和GND之间的中间状态，以降低第一N型晶体管的漏 - 源电压，然后栅极电位上升到VDD。以这种方式，避免了第一N型晶体管的漏极 - 源极电压大并且其漏极电流大的状态，使得电平移位电路的导通耐受电压增加，从而防止分解。

5. 发明申请

US20090072622A1 LOAD DRIVE CIRCUIT, DELAY CIRCUIT, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：负载驱动电路，延迟电路和半导体器件
公开(公告)号：US20090072622A1
公开(公告)日：2009-03-19
申请号：US12172426
申请日：2008-07-14
申请人： Akihiko GOTO , Nao Miyamoto , Shinobu Yabuki , Tatsuhiro Aida
发明人： Akihiko GOTO , Nao Miyamoto , Shinobu Yabuki , Tatsuhiro Aida
IPC分类号： H02J3/14
CPC分类号： H03K3/356 , G09G3/293 , G09G3/296 , H03K17/0828 , Y10T307/461
摘要： A level shift 9, IGBT1, 2 and a AND element 10 are provided. An output DOUT is controlled to four states Hi/Lo/HiZ/artificial Hi by controlling input signals IN1, IN2, IN3, PULSE_IN. An element is protected from output short circuiting by transferring an output after a fixed time period to an artificial Hi. Furthermore NMOS are connected in parallel between two inverter circuits and the two stage of the inverter circuit is connected to the gate of NMOS. A delay circuit connecting the output of the initial state of the inverter circuit to a drain and the source of the NMOS to GND is connected to PULSE_IN of the level shift 9. Thus it is possible to almost completely eliminate temperature dependency of the delay time.
摘要翻译：提供电平位移9，IGBT1,2和AND元件10。通过控制输入信号IN1，IN2，IN3，PULSE_IN，将输出DOUT控制为四个状态Hi / Lo / HiZ /人工Hi。通过将固定时间段之后的输出传送到人造Hi来保护元件免于输出短路。此外，NMOS在两个反相器电路之间并联连接，反相器电路的两级连接到NMOS的栅极。将逆变器电路的初始状态的输出连接到漏极和NMOS至GND的源极的延迟电路连接到电平移位9的PULSE_IN。因此可以几乎完全消除延迟时间的温度依赖性。

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