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    • 3. 发明授权
    • Integrated circuit free from accumulation of duty ratio errors
    • 集成电路没有占空比误差累积
    • US07180512B2
    • 2007-02-20
    • US10335925
    • 2003-01-03
    • Masao KumagaiHideto FukudaShinya Udo
    • Masao KumagaiHideto FukudaShinya Udo
    • G09G5/00G09G5/10G09G3/34G09G3/36
    • G09G3/3688
    • An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.
    • 集成电路包括:第一信号反相切换电路,其接收从其外部提供的信号作为第一输入信号,随后响应于开关信号的第一状态而在其逻辑反相之后输出第一输入信号,并输出 响应于切换信号的第二状态而没有逻辑反转的第一输入信号,基于第一信号反相切换电路的输出执行信号处理的信号处理电路和接收输出的第二信号反相切换电路 通过信号处理电路作为第二输入信号的第一信号反相切换电路,随后响应于切换信号的第二状态而在其逻辑反相之后输出第二输入信号,并输出没有逻辑反转的第二输入信号 响应于开关信号的第一状态。
    • 4. 发明授权
    • Semiconductor device equipped with transfer circuit for cascade connection
    • 配备有用于级联连接的传输电路的半导体器件
    • US06847346B2
    • 2005-01-25
    • US10278883
    • 2002-10-24
    • Masao KumagaiShinya Udo
    • Masao KumagaiShinya Udo
    • G02F1/133G09G3/20G09G3/36
    • G09G3/3685
    • A transfer circuit 25 includes two sets of an input circuit 52A and an output circuit 53B, which allows bidirectional transfer. The input circuit 52A decomposes external input data signals DI11A and DI12A to signals on lines L11 to L14 in synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuit 53B composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DO11B and DO12B. Signals on either the lines L11 to L14 or L21 to L24 are selected by a multiplexer 57 to provide to a main body circuit.
    • 传送电路25包括两组输入电路52A和输出电路53B,其允许双向传送。 输入电路52A与时钟信号CLK同步地将外部输入数据信号DI11A和DI12A分解为线路L11至L14上的信号,以便降低其频率。 输出电路53B与时钟信号CLK同步地构成分解信号,以再生原​​始信号并将其作为外部输出数据信号DO11B和DO12B输出。 在线路L11至L14或L21至L24上的信号由多路复用器57选择以提供给主体电路。
    • 5. 发明申请
    • CONTROL CIRCUIT, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING POWER SUPPLY
    • 控制电路,电子设备和控制电源的方法
    • US20120212195A1
    • 2012-08-23
    • US13328775
    • 2011-12-16
    • Koichiro KushidaKazuyoshi FutamuraMasao Kumagai
    • Koichiro KushidaKazuyoshi FutamuraMasao Kumagai
    • G05F1/46
    • H02M3/1588H02M2003/1566Y02B70/1466
    • A control circuit arranged in a power supply including first and second switches to control an output voltage of the power supply. The control circuit includes a first control circuit that switches the first and second switches in a complementary manner in accordance with a comparison result of a first reference voltage and a feedback voltage corresponding to the output voltage of the power supply. A first comparison circuit compares the output voltage or feedback voltage with a second reference value. A second comparison circuit compares a coupling point current flowing through a coupling point between the first and second switches with a third reference value. A second control circuit disables complementary switching of the first and second switches in accordance with an output signal from the first comparison circuit and enables the complementary switching in accordance with an output signal of the second comparison circuit.
    • 一种布置在电源中的控制电路,包括第一和第二开关以控制电源的输出电压。 控制电路包括第一控制电路,其根据第一参考电压和对应于电源的输出电压的反馈电压的比较结果互补地切换第一和第二开关。 第一比较电路将输出电压或反馈电压与第二参考值进行比较。 第二比较电路将流过第一和第二开关之间的耦合点的耦合点电流与第三参考值进行比较。 第二控制电路根据来自第一比较电路的输出信号禁止第一和第二开关的互补开关,并根据第二比较电路的输出信号实现互补开关。
    • 9. 发明授权
    • Magnetic head assembly for double-sided disk drive apparatus
    • 用于双面磁盘驱动装置的磁头组件
    • US4835642A
    • 1989-05-30
    • US229749
    • 1988-08-03
    • Masatoshi FurukawaMasao KumagaiTadami SugawaraHatsuo SasakiYuichi HishiAtsushi Takahashi
    • Masatoshi FurukawaMasao KumagaiTadami SugawaraHatsuo SasakiYuichi HishiAtsushi Takahashi
    • G11B17/32G11B5/48G11B5/58G11B21/20
    • G11B5/58G11B5/4833
    • A magnetic head assembly including a carriage which carries thereon a first magnetic head for information writing and reading to and from one side of a disc-like magnetic recording medium, and a hold case which carries thereon a second magnetic head for information writing and reading to and from the other side of the magnetic recording medium, the second magnetic head being disposed in a position opposed to the first magnetic head, the hold case being connected to the carriage through hinge means rotatably to a certain degree relative to the carriage, and the magnetic head assembly being reciprocated in a radial direction of the magnetic recording medium. The first magnetic head is mounted on the carriage through a gimbal spring which is formed rotatably to a certain degree with respect to biaxial hinge portions, and the second magnetic head is mounted on the hold case through a spring plate which is formed rotatably to a certain degree with respect to a uniaxial hinge portion. The hold case is urged toward the carriage on the side of the hinge means rotatably to a certain degree relative to the carriage.
    • 一种磁头组件,包括:托架,其承载有用于向盘状磁记录介质的一侧进行信息写入和读取的第一磁头;以及保持壳体,其承载用于信息写入和读取的第二磁头 并且从磁记录介质的另一侧开始,第二磁头设置在与第一磁头相对的位置,保持壳体通过铰链装置通过铰链装置相对于滑架可旋转地连接到一定程度, 磁头组件在磁记录介质的径向方向上往复运动。 第一磁头通过相对于双轴铰链部可旋转地形成一定程度的万向弹簧安装在滑架上,第二磁头通过弹簧板安装在保持壳上,弹簧板可旋转地形成一定的 相对于单轴铰链部分。 保持壳体相对于滑架以一定程度的旋转自如地被推向铰链装置侧的滑架。