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1. 发明授权

US5511201A Data processing apparatus, power supply controller and display unit 失效
标题翻译：数据处理装置，电源控制器和显示单元
公开(公告)号：US5511201A
公开(公告)日：1996-04-23
申请号：US857629
申请日：1992-03-25
申请人： Hideki Kamimaki , Kiyokazu Nishioka , Tsuguji Tachiuchi , Nobuo Tsuchiya , Masahiro Jinushi , Hitoshi Sadamitsu , Hiroshi Ito , Takashi Yoshitomi , Koichi Isaji , Takao Ohba
发明人： Hideki Kamimaki , Kiyokazu Nishioka , Tsuguji Tachiuchi , Nobuo Tsuchiya , Masahiro Jinushi , Hitoshi Sadamitsu , Hiroshi Ito , Takashi Yoshitomi , Koichi Isaji , Takao Ohba
IPC分类号： G09G3/34 , G06F11/00 , G06F11/30
CPC分类号： G09G3/3406 , G09G2320/0606 , G09G2320/0626 , G09G2330/021 , G09G2330/026
摘要： A data processing apparatus which includes a display unit and a power supply controller for supplying power to the display unit. The display unit has a display screen and a back light controller. The power supply controller comprises a switch, at least one output line for receiving the power from the switch and for supplying therethrough the power to electronic devices, a delay circuit for receiving the power from the switch and when the switch is turned ON to start supply of the power, for outputting the power after passage of a predetermined time from the start of the power supply, and a second output line for supplying the power from the delay circuit to the back light controller therethrough. The display unit has a memory means for storing therein a luminance data on the display screen through the back light controller when the power supply is turned OFF and for determining an output state of the display unit through the back light controller on the basis of the luminance data read out from the memory means when the power supply is turned ON. Further, the data processing apparatus has a means for invalidating output of a display data to be output onto the display screen and a means, after the display data is invalidated, for reducing a frequency of a timing signal or invalidating output of the timing signal for the display unit.
摘要翻译：一种数据处理装置，包括显示单元和用于向显示单元供电的电源控制器。显示单元具有显示屏和背光控制器。电源控制器包括开关，至少一个输出线，用于从开关接收电力并通过其向电子设备提供电力;延迟电路，用于从开关接收电力;以及当开关接通以开始供电时的功率，用于在从电源开始经过预定时间之后输出电力;以及第二输出线，用于将来自延迟电路的电力提供给背光控制器。显示单元具有存储装置，用于当电源关闭时通过背光控制器在其上存储亮度数据，并且通过背光控制器基于亮度来确定显示单元的输出状态当电源接通时，从存储器读出的数据意味着。此外，数据处理装置具有使输出到显示屏幕上的显示数据的输出无效的装置和在显示数据无效之后的装置，用于减少定时信号的频率或使定时信号的输出无效，显示单元。

2. 发明授权

US5193196A Process request arbitration system which preferentially maintains previously selected process request upon receipt of a subsequent request of identical priority 失效
标题翻译：处理请求仲裁系统，其在接收到相同优先级的后续请求时优先维护先前选择的进程请求
公开(公告)号：US5193196A
公开(公告)日：1993-03-09
申请号：US331297
申请日：1989-03-31
申请人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
发明人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
IPC分类号： G06F13/30 , G06F13/364
CPC分类号： G06F13/30 , G06F13/364
摘要： A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.
摘要翻译：从处理单元产生的多个处理请求，例如直接存储器访问（DMA）信道由优先级电路根据分配给每个处理单元的优先级控制。最高优先级获得的处理单元及其优先级的信息被存储在锁存器中。禁止具有与存储的处理单元相同的优先级的另一处理请求被提供给偏好电路，使得在接受具有相同优先级的另一进程请求之前接受并执行第一生成的处理请求。

3. 发明授权

US5301294A Address bus control system 失效
标题翻译：地址总线控制系统
公开(公告)号：US5301294A
公开(公告)日：1994-04-05
申请号：US689556
申请日：1991-04-23
申请人： Takahiro Kawai , Masatsugu Shinozaki , Hitoshi Sadamitsu , Tadashi Kyoda , Katsuya Takanashi , Hironori Uchida
发明人： Takahiro Kawai , Masatsugu Shinozaki , Hitoshi Sadamitsu , Tadashi Kyoda , Katsuya Takanashi , Hironori Uchida
IPC分类号： G06F13/14 , G06F12/02 , G06F12/06
CPC分类号： G06F12/0223 , G06F12/0661
摘要： An address bus control system is provided of the type in which a controller including a central processing unit is connected through an address bus and a data bus to hardware modules which control equipment to be controlled. An address space defined by an address bus includes a discrimination space for discriminating the attribute of the hardware module and a function space for allocating and clearing an address space for a function interface of the hardware module. The attribute of a hardware module connected to a connector having a corresponding address is recognized using the discrimination space. The function interface of each hardware module is assigned a space within the function space in accordance with the contents of the discrimination space in concern, or the assigned space is canceled. An address of the function space can be allocated to only a necessary function interface, merely by connecting the hardware module to the connector, allowing to set up hardware modules equal to or larger than the total address space.
摘要翻译：提供地址总线控制系统，其中包括中央处理单元的控制器通过地址总线和数据总线连接到控制要控制的设备的硬件模块。由地址总线定义的地址空间包括用于识别硬件模块的属性的鉴别空间和用于分配和清除硬件模块的功能接口的地址空间的功能空间。使用识别空间来识别连接到具有相应地址的连接器的硬件模块的属性。每个硬件模块的功能接口根据关注的鉴别空间的内容在功能空间内分配一个空间，或者分配的空间被取消。仅通过将硬件模块连接到连接器，可以将功能空间的地址分配给必要的功能接口，允许设置等于或大于总地址空间的硬件模块。

4. 发明授权

US4959770A Data processing system employing two address translators, allowing rapid access to main storage by input/output units 失效
标题翻译：数据处理系统采用两个地址转换器，允许通过输入/输出单元快速访问主存储
公开(公告)号：US4959770A
公开(公告)日：1990-09-25
申请号：US52870
申请日：1987-05-22
申请人： Megumu Kondo , Shuji Kamiya , Kazuhiko Fukuoka , Masatsugu Shinozaki , Hitoshi Sadamitsu
发明人： Megumu Kondo , Shuji Kamiya , Kazuhiko Fukuoka , Masatsugu Shinozaki , Hitoshi Sadamitsu
IPC分类号： G06F12/02 , G06F12/10 , G06F13/12
CPC分类号： G06F12/1081
摘要： In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit. In this configuration, the second address translation unit, to translate an address from the input/output unit, is disposed at an input to the memory, which eliminates the necessity for a translator on the side of the input/output device.
摘要翻译：在具有中央处理单元的数据处理系统中，至少包括诸如MT单元或软盘单元的输入/输出单元，存储器，地址总线，第一地址转换单元，第二地址转换单元和地址选择单元，来自中央处理单元的输出地址由第一地址转换单元转换以将结果地址提供给地址总线，并且将来自输入/输出单元的输出地址直接馈送到地址总线。地址总线上的地址被传送到地址选择单元，地址选择单元选择性地向存储器提供从第一平移单元传送到地址总线上的输出地址，或者通过将输出地址从输入/输出单元。在该配置中，将来自输入/输出单元的地址转换的第二地址转换单元设置在存储器的输入端，这消除了在输入/输出设备侧的翻译器的必要性。

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