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1. 发明授权

US5193196A Process request arbitration system which preferentially maintains previously selected process request upon receipt of a subsequent request of identical priority 失效
标题翻译：处理请求仲裁系统，其在接收到相同优先级的后续请求时优先维护先前选择的进程请求
公开(公告)号：US5193196A
公开(公告)日：1993-03-09
申请号：US331297
申请日：1989-03-31
申请人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
发明人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
IPC分类号： G06F13/30 , G06F13/364
CPC分类号： G06F13/30 , G06F13/364
摘要： A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.
摘要翻译：从处理单元产生的多个处理请求，例如直接存储器访问（DMA）信道由优先级电路根据分配给每个处理单元的优先级控制。最高优先级获得的处理单元及其优先级的信息被存储在锁存器中。禁止具有与存储的处理单元相同的优先级的另一处理请求被提供给偏好电路，使得在接受具有相同优先级的另一进程请求之前接受并执行第一生成的处理请求。

2. 发明授权

US5276818A Bus system for information processing system and method of controlling the same 失效
标题翻译：信息处理系统总线系统及其控制方法
公开(公告)号：US5276818A
公开(公告)日：1994-01-04
申请号：US512810
申请日：1990-04-20
申请人： Koichi Okazawa , Hiroaki Aotsu , Hitoshi Kawaguchi , Masami Jikihara , Kazushi Kobayashi , Koichi Kimura , Tetsuya Mochida
发明人： Koichi Okazawa , Hiroaki Aotsu , Hitoshi Kawaguchi , Masami Jikihara , Kazushi Kobayashi , Koichi Kimura , Tetsuya Mochida
IPC分类号： G06F13/28 , G06F13/36 , G06F13/364 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4217 , G06F13/364
摘要： A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.
摘要翻译：一种用于信息处理系统的总线系统，其中在公共总线上控制多个模块之间的数据传输。响应于来自模块的总线使用请求，发出用于中止由具有较低优先级的另一模块执行的数据传输的命令。正在传送数据的模块通过发出一个指示要传送的字是最终字的信号来响应中止命令。通过与从总线控制器提供的时钟同步的与数据具有相同宽度的地址总线，在主机和从机之间传送数据。

3. 发明授权

US5148539A Address bus control apparatus 失效
标题翻译：地址总线控制装置
公开(公告)号：US5148539A
公开(公告)日：1992-09-15
申请号：US711254
申请日：1991-06-04
申请人： Hiromichi Enomoto , Kazushi Kobayashi , Masami Jikihara , Norihisa Amako
发明人： Hiromichi Enomoto , Kazushi Kobayashi , Masami Jikihara , Norihisa Amako
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
摘要： An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.
摘要翻译：地址总线控制装置连接与CPU和存储器单元连接的存储器总线以及与输入/输出单元连接的系统总线。系统总线的地址总线宽度小于存储器总线的地址总线宽度，其中一个输入/输出单元是使用比用于访问另一个单元的系统总线的地址总线宽度更小的地址数据的主单元。地址总线控制装置，当来自主单元的总线识别信息识别存储器总线时，将第一互补地址数据与来自主单元的地址数据一起传递到存储器总线上，并且当总线识别信息识别系统总线时，传送第二补充地址数据到系统总线上，从而确保每个总线必要的地址数据宽度。

4. 发明授权

US07802045B2 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US07802045B2
公开(公告)日：2010-09-21
申请号：US12501684
申请日：2009-07-13
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

5. 发明授权

US07577781B2 Bus system for use with information processing apparatus 失效
公开(公告)号：US07577781B2
公开(公告)日：2009-08-18
申请号：US12155047
申请日：2008-05-29
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

6. 发明授权

US07398346B2 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US07398346B2
公开(公告)日：2008-07-08
申请号：US11543878
申请日：2006-10-06
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

7. 发明授权

US5889971A Bus system for use with information processing apparatus 失效
公开(公告)号：US5889971A
公开(公告)日：1999-03-30
申请号：US959913
申请日：1997-10-29
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

8. 发明授权

US5483642A Bus system for use with information processing apparatus 失效
公开(公告)号：US5483642A
公开(公告)日：1996-01-09
申请号：US311893
申请日：1994-09-26
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

9. 发明授权

US06907489B2 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US06907489B2
公开(公告)日：2005-06-14
申请号：US10787110
申请日：2004-02-27
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

10. 发明授权

US5935231A Bus system for use with information processing apparatus 有权
公开(公告)号：US5935231A
公开(公告)日：1999-08-10
申请号：US143985
申请日：1998-08-31
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/16 , G06F12/00 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

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