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1. 发明申请

US20100314690A1 Sidewall-Free CESL for Enlarging ILD Gap-Fill Window 审中-公开
标题翻译：用于扩大ILD缺口填充窗口的无侧壁CESL
公开(公告)号：US20100314690A1
公开(公告)日：2010-12-16
申请号：US12750485
申请日：2010-03-30
申请人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Hun-Jan Tao
发明人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Hun-Jan Tao
IPC分类号： H01L27/088
CPC分类号： H01L21/28017 , H01L21/76829 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L27/088 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , Y10S438/97 , H01L2924/00
摘要： An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
摘要翻译：集成电路结构包括第一栅极条; 在第一栅极条的侧壁上的栅极间隔物; 以及具有比栅极间隔物的顶表面低的底部的接触蚀刻停止层（CESL），其中栅极间隔物的侧壁的一部分没有形成CESL。

2. 发明授权

US08299508B2 CMOS structure with multiple spacers 有权
标题翻译：具有多个间隔物的CMOS结构
公开(公告)号：US08299508B2
公开(公告)日：2012-10-30
申请号：US12757517
申请日：2010-04-09
申请人： Bor Chiuan Hsieh , Han-Ping Chung , Chih-Hsin Ko , Bor-Wen Chan , Hun-Jan Tao
发明人： Bor Chiuan Hsieh , Han-Ping Chung , Chih-Hsin Ko , Bor-Wen Chan , Hun-Jan Tao
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
摘要翻译：半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔第一栅极间隔物的侧壁。

3. 发明申请

US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
标题翻译：蚀刻过程避免多晶硅缺口
公开(公告)号：US20060154487A1
公开(公告)日：2006-07-13
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/8234 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

4. 发明授权

US08372755B2 Multilayer hard mask 有权
标题翻译：多层硬掩模
公开(公告)号：US08372755B2
公开(公告)日：2013-02-12
申请号：US12686866
申请日：2010-01-13
申请人： Shiang-Bau Wang , Hun-Jan Tao
发明人： Shiang-Bau Wang , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

5. 发明申请

US20080093675A1 MOS devices with continuous contact etch stop layer 有权
标题翻译：具有连续接触蚀刻停止层的MOS器件
公开(公告)号：US20080093675A1
公开(公告)日：2008-04-24
申请号：US11583634
申请日：2006-10-18
申请人： Liang-Gi Yao , Shiang-Bau Wang , Huan-Just Lin , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Liang-Gi Yao , Shiang-Bau Wang , Huan-Just Lin , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/76
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823842 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.
摘要翻译：半导体结构包括衬底，衬底上的栅极堆叠，与栅极堆叠相邻的源极/漏极区域，源极/漏极区域上的源极/漏极硅化物区域，源极/漏极硅化物区域上的保护层，其中栅极叠层上的区域基本上没有保护层，以及在保护层上方并且在栅极堆叠上延伸的接触蚀刻停止层（CESL）。

6. 发明授权

US07301645B2 In-situ critical dimension measurement 有权
标题翻译：原位临界尺寸测量
公开(公告)号：US07301645B2
公开(公告)日：2007-11-27
申请号：US11053300
申请日：2005-02-07
申请人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
发明人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
IPC分类号： G01B11/02
CPC分类号： H01L22/20
摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.
摘要翻译：提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

7. 发明授权

US07732878B2 MOS devices with continuous contact etch stop layer 有权
标题翻译：具有连续接触蚀刻停止层的MOS器件
公开(公告)号：US07732878B2
公开(公告)日：2010-06-08
申请号：US11583634
申请日：2006-10-18
申请人： Liang-Gi Yao , Shiang-Bau Wang , Huan-Just Lin , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Liang-Gi Yao , Shiang-Bau Wang , Huan-Just Lin , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/78
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823842 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.
摘要翻译：半导体结构包括衬底，衬底上的栅极堆叠，与栅极堆叠相邻的源极/漏极区域，源极/漏极区域上的源极/漏极硅化物区域，源极/漏极硅化物区域上的保护层，其中栅极叠层上的区域基本上没有保护层，以及在保护层上方并且在栅极堆叠上延伸的接触蚀刻停止层（CESL）。

8. 发明申请

US20060046323A1 In-situ critical dimension measrument 有权
标题翻译：原位关键维度测量
公开(公告)号：US20060046323A1
公开(公告)日：2006-03-02
申请号：US11053300
申请日：2005-02-07
申请人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
发明人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.
摘要翻译：提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

9. 发明申请

US20110171804A1 Multilayer Hard Mask 有权
标题翻译：多层硬面膜
公开(公告)号：US20110171804A1
公开(公告)日：2011-07-14
申请号：US12686866
申请日：2010-01-13
申请人： Shiang-Bau Wang , Hun-Jan Tao
发明人： Shiang-Bau Wang , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

10. 发明授权

US07109085B2 Etching process to avoid polysilicon notching 有权
标题翻译：蚀刻工艺避免多晶硅切口
公开(公告)号：US07109085B2
公开(公告)日：2006-09-19
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

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