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1. 发明授权

US07947551B1 Method of forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US07947551B1
公开(公告)日：2011-05-24
申请号：US12892331
申请日：2010-09-28
申请人： Sen-Hong Syue , Bor Chiuan Hsieh , Shiang-Bau Wang
发明人： Sen-Hong Syue , Bor Chiuan Hsieh , Shiang-Bau Wang
IPC分类号： H01L21/00
CPC分类号： H01L21/02337 , H01L21/02274 , H01L21/02282 , H01L21/02356 , H01L21/76224
摘要： An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.
摘要翻译：本公开的实施例包括形成浅沟槽隔离结构的方法。提供基板。衬底包括顶表面。形成沟槽以从顶表面延伸到衬底中。沟槽具有侧壁和底面。在侧壁和底表面上形成硅衬层。可流动介电材料填充在沟槽中。进行退火处理以使可流动电介质材料致密化并同时将硅衬层转化为氧化硅层。

2. 发明申请

US20110084355A1 Isolation Structure For Semiconductor Device 审中-公开
标题翻译：半导体器件的隔离结构
公开(公告)号：US20110084355A1
公开(公告)日：2011-04-14
申请号：US12576818
申请日：2009-10-09
申请人： Hsien-Hsin Lin , Bor Chiuan Hsieh , Chen-Ping Chen
发明人： Hsien-Hsin Lin , Bor Chiuan Hsieh , Chen-Ping Chen
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/0237 , H01L21/02381 , H01L21/02639
摘要： A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region.
摘要翻译：提供半导体器件。半导体器件包括衬底，设置在衬底上的隔离特征以及邻近隔离特征设置的有源区。隔离特征可以是浅沟槽隔离特征。 STI特征在特征顶部具有第一宽度，并且在特征底部具有第二宽度。第一宽度小于第二宽度。还提供了制造半导体器件的方法。一种方法包括形成浅沟槽隔离特征，然后生长与STI特征相邻的外延层以形成有源区。

3. 发明申请

US20100314690A1 Sidewall-Free CESL for Enlarging ILD Gap-Fill Window 审中-公开
标题翻译：用于扩大ILD缺口填充窗口的无侧壁CESL
公开(公告)号：US20100314690A1
公开(公告)日：2010-12-16
申请号：US12750485
申请日：2010-03-30
申请人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Hun-Jan Tao
发明人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Hun-Jan Tao
IPC分类号： H01L27/088
CPC分类号： H01L21/28017 , H01L21/76829 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L27/088 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , Y10S438/97 , H01L2924/00
摘要： An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
摘要翻译：集成电路结构包括第一栅极条; 在第一栅极条的侧壁上的栅极间隔物; 以及具有比栅极间隔物的顶表面低的底部的接触蚀刻停止层（CESL），其中栅极间隔物的侧壁的一部分没有形成CESL。

4. 发明授权

US08609497B2 Method of dual EPI process for semiconductor device 有权
标题翻译：半导体器件的双重EPI工艺方法
公开(公告)号：US08609497B2
公开(公告)日：2013-12-17
申请号：US12721399
申请日：2010-03-10
申请人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Ming-Jie Huang
发明人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Ming-Jie Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/82385 , H01L21/823864 , H01L21/845 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括分别在衬底的第一和第二区域上形成第一和第二栅极结构，在第一和第二栅极结构的侧壁上形成间隔物，间隔物由第一材料形成在所述第一和第二栅极结构上形成覆盖层，所述覆盖层由不同于所述第一材料的第二材料形成，在所述第二区域上形成保护层以保护所述第二栅极结构，在所述第一栅极结构上移除所述覆盖层门结构; 在所述第二区域上去除所述保护层，在所述第一区域中外延（epi）在所述衬底的暴露部分上生长半导体材料，以及通过蚀刻工艺去除所述第二栅极结构上的所述覆盖层，所述蚀刻工艺显示所述第二区域的蚀刻选择性材料到第一种材料。

5. 发明申请

US20110201164A1 Method of Dual EPI Process For Semiconductor Device 有权
标题翻译：半导体器件的双重EPI工艺方法
公开(公告)号：US20110201164A1
公开(公告)日：2011-08-18
申请号：US12721399
申请日：2010-03-10
申请人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Ming-Jie Huang
发明人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Ming-Jie Huang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823487 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/82385 , H01L21/823864 , H01L21/845 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括分别在衬底的第一和第二区域上形成第一和第二栅极结构，在第一和第二栅极结构的侧壁上形成间隔物，间隔物由第一材料形成在所述第一和第二栅极结构上形成覆盖层，所述覆盖层由不同于所述第一材料的第二材料形成，在所述第二区域上形成保护层以保护所述第二栅极结构，在所述第一栅极结构上移除所述覆盖层门结构; 在所述第二区域上去除所述保护层，在所述第一区域中外延（epi）在所述衬底的暴露部分上生长半导体材料，以及通过蚀刻工艺去除所述第二栅极结构上的所述覆盖层，所述蚀刻工艺显示所述第二区域的蚀刻选择性材料到第一种材料。

6. 发明申请

US20110031538A1 CMOS STRUCTURE WITH MULTIPLE SPACERS 有权
标题翻译： CMOS结构与多个间隔
公开(公告)号：US20110031538A1
公开(公告)日：2011-02-10
申请号：US12757517
申请日：2010-04-09
申请人： Bor Chiuan HSIEH , Han-Ping CHUNG , Chih-Hsin KO , Bor-Wen CHAN , Hun-Jan TAO
发明人： Bor Chiuan HSIEH , Han-Ping CHUNG , Chih-Hsin KO , Bor-Wen CHAN , Hun-Jan TAO
IPC分类号： H01L29/78 , H01L29/49
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
摘要翻译：半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔物第一栅极间隔物的侧壁。

7. 发明授权

US08299508B2 CMOS structure with multiple spacers 有权
标题翻译：具有多个间隔物的CMOS结构
公开(公告)号：US08299508B2
公开(公告)日：2012-10-30
申请号：US12757517
申请日：2010-04-09
申请人： Bor Chiuan Hsieh , Han-Ping Chung , Chih-Hsin Ko , Bor-Wen Chan , Hun-Jan Tao
发明人： Bor Chiuan Hsieh , Han-Ping Chung , Chih-Hsin Ko , Bor-Wen Chan , Hun-Jan Tao
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
摘要翻译：半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔第一栅极间隔物的侧壁。

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