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1. 发明授权

US09945048B2 Semiconductor structure and method 有权
公开(公告)号：US09945048B2
公开(公告)日：2018-04-17
申请号：US13525041
申请日：2012-06-15
申请人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
发明人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
IPC分类号： C30B15/04 , H01L21/02 , C30B15/20 , C30B31/02 , C30B31/04 , H01L21/311 , C30B15/22 , H01L29/36 , H01L21/762 , C30B31/16 , H01L21/3105 , C30B29/06 , H01L21/322 , C30B15/00 , C30B33/00 , H01L29/78
CPC分类号： C30B15/04 , C30B15/00 , C30B15/203 , C30B15/206 , C30B15/22 , C30B29/06 , C30B31/02 , C30B31/04 , C30B31/165 , C30B33/00 , H01L21/0201 , H01L21/31053 , H01L21/311 , H01L21/3225 , H01L21/76224 , H01L29/365 , H01L29/78
摘要： A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

2. 发明授权

US08604562B2 Post CMP planarization by cluster ion beam etch 有权
标题翻译：通过簇离子束蚀刻后CMP平坦化
公开(公告)号：US08604562B2
公开(公告)日：2013-12-10
申请号：US13466569
申请日：2012-05-08
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： H01L29/00
CPC分类号： H01L21/31055 , H01L21/3065 , H01L21/31116 , H01L21/32115 , H01L21/32136 , H01L21/76229 , H01L21/76819 , H01L22/12 , H01L22/20
摘要： The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.
摘要翻译：所描述的机构的实施例使得能够改善衬底的平面性，这对于图案化和器件产量提高至关重要。在达到最终厚度之前或在所有去除膜被抛光之前，使用化学机械抛光（CMP）去除膜以使基板平坦化。然后测量衬底的形貌和膜厚度。气体簇离子束（GCIB）蚀刻工具使用地形和厚度数据来确定在特定位置上要移除多少胶片。 GCIB蚀刻可以去除最终层，以满足基板均匀性和厚度目标的要求。这些机制可以提高平面性，以满足先进的处理技术的要求。

3. 发明授权

US08361338B2 Hard mask removal method 有权
标题翻译：硬掩模去除方法
公开(公告)号：US08361338B2
公开(公告)日：2013-01-29
申请号：US12704032
申请日：2010-02-11
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： C23F1/00 , B44C1/22
CPC分类号： H01L21/02107 , H01L21/02071 , H01L21/02697 , H01L21/31055 , H01L21/31111 , H01L21/31116 , H01L21/32139
摘要： The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.
摘要翻译：在本公开中描述的用于在蚀刻栅极叠层之后去除栅极堆叠的多晶硅层上的硬掩模层的方法的实施例允许在没有光刻的帮助下完全去除硬掩模层。电介质材料沉积在衬底上，栅极叠层。首先通过化学机械抛光去除衬底的形貌。之后，使用蚀刻气体（或蒸汽）来蚀刻剩余介电层和硬掩模层的一部分。蚀刻气体形成沉积在衬底表面上的蚀刻副产物，随后可通过加热除去。重复蚀刻和加热去除蚀刻副产物，直到硬掩模层完成去除。之后，通过湿蚀刻除去剩余的介电层。与常规的硬掩模去除方法相比，所描述的方法更简单并且更便宜。

4. 发明申请

US20120205746A1 END-TO-END GAP FILL USING DIELECTRIC FILM 有权
标题翻译：使用电介质膜的端到端胶带填充
公开(公告)号：US20120205746A1
公开(公告)日：2012-08-16
申请号：US13025414
申请日：2011-02-11
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/28 , H01L21/76837
摘要： A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成多个栅极结构。多个栅极结构被布置成多条线，其中线之间的端对端间隔小于线之间的线间间隔。该方法还包括在栅极结构上形成蚀刻停止层，在栅极结构之上形成层间电介质，以及在形成层间电介质之前在栅极结构上形成电介质膜。电介质膜在形成在门结构之间的端到端间隔中的端到端间隙中融合。

5. 发明授权

US08193094B2 Post CMP planarization by cluster ION beam etch 有权
标题翻译：通过簇ION光束蚀刻后CMP平坦化
公开(公告)号：US08193094B2
公开(公告)日：2012-06-05
申请号：US12819743
申请日：2010-06-21
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31055 , H01L21/3065 , H01L21/31116 , H01L21/32115 , H01L21/32136 , H01L21/76229 , H01L21/76819 , H01L22/12 , H01L22/20
摘要： The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.
摘要翻译：所描述的机构的实施例使得能够改善衬底的平面性，这对于图案化和器件产量提高至关重要。在达到最终厚度之前或在所有去除膜被抛光之前，使用化学机械抛光（CMP）去除膜以使基板平坦化。然后测量衬底的形貌和膜厚度。气体簇离子束（GCIB）蚀刻工具使用地形和厚度数据来确定在特定位置上要移除多少胶片。 GCIB蚀刻可以去除最终层，以满足基板均匀性和厚度目标的要求。这些机制可以提高平面性，以满足先进的处理技术的要求。

6. 发明申请

US20120003806A1 METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造集成电路装置的方法
公开(公告)号：US20120003806A1
公开(公告)日：2012-01-05
申请号：US12827936
申请日：2010-06-30
申请人： Shiang-Bau WANG
发明人： Shiang-Bau WANG
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/823864 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/6656 , H01L29/6659
摘要： A method for fabricating an integrated device is disclosed. A sacrificial gate stack is provided with a line width narrower than the target width of the final gate structure. After performing a tilt-angle implantation process, L-shape spacers are formed over the sidewalls of the sacrificial gate stack, and offset spacers are formed over the sidewalls of the L-shape spacers. An insulating layer is formed over the offset spacers and the substrate. Then, the sacrificial gate stack and the L-shape spacers are removed to form a trench in the insulating layer. A metal gate is then filled in the trench to form the final gate structure.
摘要翻译：公开了一种用于制造集成器件的方法。牺牲栅极堆叠设置有比最终栅极结构的目标宽度窄的线宽。在进行倾斜角度注入工艺之后，在牺牲栅极堆叠的侧壁上形成L形间隔物，并且在L形间隔物的侧壁上形成偏移间隔物。绝缘层形成在偏置间隔物和衬底上。然后，去除牺牲栅极堆叠和L形间隔物以在绝缘层中形成沟槽。然后将金属栅极填充在沟槽中以形成最终的栅极结构。

7. 发明申请

US20110195575A1 NOVEL HARD MASK REMOVAL METHOD 有权
标题翻译：新型硬面罩拆卸方法
公开(公告)号：US20110195575A1
公开(公告)日：2011-08-11
申请号：US12704032
申请日：2010-02-11
申请人： Shiang-Bau WANG
发明人： Shiang-Bau WANG
IPC分类号： H01L21/465
CPC分类号： H01L21/02107 , H01L21/02071 , H01L21/02697 , H01L21/31055 , H01L21/31111 , H01L21/31116 , H01L21/32139
摘要： The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.
摘要翻译：在本公开中描述的用于在蚀刻栅极叠层之后去除栅极堆叠的多晶硅层上的硬掩模层的方法的实施例允许在没有光刻的帮助下完全去除硬掩模层。电介质材料沉积在衬底上，栅极叠层。首先通过化学机械抛光去除衬底的形貌。之后，使用蚀刻气体（或蒸汽）来蚀刻剩余介电层和硬掩模层的一部分。蚀刻气体形成沉积在衬底表面上的蚀刻副产物，随后可通过加热除去。重复蚀刻和加热去除蚀刻副产物，直到硬掩模层完成去除。之后，通过湿蚀刻除去剩余的介电层。与常规的硬掩模去除方法相比，所描述的方法更简单并且更便宜。

8. 发明授权

US07947551B1 Method of forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US07947551B1
公开(公告)日：2011-05-24
申请号：US12892331
申请日：2010-09-28
申请人： Sen-Hong Syue , Bor Chiuan Hsieh , Shiang-Bau Wang
发明人： Sen-Hong Syue , Bor Chiuan Hsieh , Shiang-Bau Wang
IPC分类号： H01L21/00
CPC分类号： H01L21/02337 , H01L21/02274 , H01L21/02282 , H01L21/02356 , H01L21/76224
摘要： An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.
摘要翻译：本公开的实施例包括形成浅沟槽隔离结构的方法。提供基板。衬底包括顶表面。形成沟槽以从顶表面延伸到衬底中。沟槽具有侧壁和底面。在侧壁和底表面上形成硅衬层。可流动介电材料填充在沟槽中。进行退火处理以使可流动电介质材料致密化并同时将硅衬层转化为氧化硅层。

9. 发明申请

US20100314690A1 Sidewall-Free CESL for Enlarging ILD Gap-Fill Window 审中-公开
标题翻译：用于扩大ILD缺口填充窗口的无侧壁CESL
公开(公告)号：US20100314690A1
公开(公告)日：2010-12-16
申请号：US12750485
申请日：2010-03-30
申请人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Hun-Jan Tao
发明人： Han-Pin Chung , Bor Chiuan Hsieh , Shiang-Bau Wang , Hun-Jan Tao
IPC分类号： H01L27/088
CPC分类号： H01L21/28017 , H01L21/76829 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L27/088 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , Y10S438/97 , H01L2924/00
摘要： An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
摘要翻译：集成电路结构包括第一栅极条; 在第一栅极条的侧壁上的栅极间隔物; 以及具有比栅极间隔物的顶表面低的底部的接触蚀刻停止层（CESL），其中栅极间隔物的侧壁的一部分没有形成CESL。

10. 发明申请

US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
标题翻译：蚀刻过程避免多晶硅缺口
公开(公告)号：US20060154487A1
公开(公告)日：2006-07-13
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/8234 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

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