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1. 发明授权

US07109085B2 Etching process to avoid polysilicon notching 有权
标题翻译：蚀刻工艺避免多晶硅切口
公开(公告)号：US07109085B2
公开(公告)日：2006-09-19
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

2. 发明申请

US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
标题翻译：蚀刻过程避免多晶硅缺口
公开(公告)号：US20060154487A1
公开(公告)日：2006-07-13
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/8234 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

3. 发明申请

US20050106888A1 Method of in-situ damage removal - post O2 dry process 审中-公开
标题翻译：原位损伤去除方法 - 后O2干法
公开(公告)号：US20050106888A1
公开(公告)日：2005-05-19
申请号：US10714207
申请日：2003-11-14
申请人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
IPC分类号： G03F7/42 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/461 , H01L21/768
CPC分类号： H01L21/31116 , G03F7/427 , H01L21/02046 , H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814
摘要： An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.
摘要翻译：公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是可以单独使用或与上述含卤素气体中的一种一起使用。氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

4. 发明申请

US20050032386A1 Etching and plasma treatment process to improve a gate profile 有权
标题翻译：蚀刻和等离子体处理工艺，提高浇口型材
公开(公告)号：US20050032386A1
公开(公告)日：2005-02-10
申请号：US10634001
申请日：2003-08-04
申请人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
发明人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/461 , H01L21/8238
CPC分类号： H01L21/823828 , H01L21/32137
摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.
摘要翻译：一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。

5. 发明申请

US20120108046A1 Patterning Methodology for Uniformity Control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US20120108046A1
公开(公告)日：2012-05-03
申请号：US13281862
申请日：2011-10-26
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/28 , H01L21/308
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

6. 发明授权

US09153440B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US09153440B2
公开(公告)日：2015-10-06
申请号：US13428923
申请日：2012-03-23
申请人： Chih-Han Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yih-Ann Lin , Jr-Jung Lin
发明人： Chih-Han Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yih-Ann Lin , Jr-Jung Lin
IPC分类号： H01L21/308 , H01L21/033 , H01L21/311 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.
摘要翻译：一种方法包括在衬底上提供第一掩模图案，形成与第一掩模图案的侧壁相邻的第一间隔物，去除第一掩模图案，形成邻接第一间隔物的侧壁的第二间隔物，在衬底上形成填充层，并且在衬底上形成第二掩模图案。

7. 发明授权

US08273632B2 Patterning methodology for uniformity control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US08273632B2
公开(公告)日：2012-09-25
申请号：US13281862
申请日：2011-10-26
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

8. 发明授权

US08053323B1 Patterning methodology for uniformity control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US08053323B1
公开(公告)日：2011-11-08
申请号：US12938571
申请日：2010-11-03
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

9. 发明授权

US06686129B2 Partial photoresist etching 有权
标题翻译：部分光刻胶蚀刻
公开(公告)号：US06686129B2
公开(公告)日：2004-02-03
申请号：US09975854
申请日：2001-10-11
申请人： Ming-Ching Chang , Hun-Jan Tao
发明人： Ming-Ching Chang , Hun-Jan Tao
IPC分类号： G03F726
CPC分类号： H01L21/0332 , H01L21/0276 , H01L21/0337 , H01L21/3081 , H01L21/31116 , H01L21/31144
摘要： Partial photoresist etching is disclosed. A film on a semiconductor wafer includes a hard mask, doped polysilicon below the hard mask, undoped polysilicon below the doped polysilicon, and a stop layer below the undoped polysilicon. Photoresist etching is performed through the hard mask and the doped polysilicon by using a photoresist mask. After the photoresist mask is removed, photoresist-free etching is performed through the undoped polysilicon through to the stop layer by using the hard mask. A semiconductor device is disclosed that may be fabricated using this partial photoresist etching process.
摘要翻译：公开了部分光致抗蚀剂蚀刻。半导体晶片上的薄膜包括硬掩模，硬掩模下方的掺杂多晶硅，掺杂多晶硅下方的未掺杂多晶硅，以及未掺杂多晶硅之下的停止层。通过使用光致抗蚀剂掩模，通过硬掩模和掺杂多晶硅进行光刻蚀蚀。在去除光致抗蚀剂掩模之后，通过使用硬掩模，通过未掺杂的多晶硅通过至停止层进行无光致抗蚀剂的蚀刻。公开了可以使用该部分光致抗蚀剂蚀刻工艺制造的半导体器件。

10. 发明授权

US06794302B1 Dynamic feed forward temperature control to achieve CD etching uniformity 失效
标题翻译：动态前馈温度控制实现CD蚀刻均匀性
公开(公告)号：US06794302B1
公开(公告)日：2004-09-21
申请号：US10393909
申请日：2003-03-20
申请人： Li-Shiun Chen , Ming-Ching Chang , Huan-Just Lin , Li-Te S. Lin , Yung-Hog Chiu , Hun-Jan Tao
发明人： Li-Shiun Chen , Ming-Ching Chang , Huan-Just Lin , Li-Te S. Lin , Yung-Hog Chiu , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01J37/32935 , H01L21/32135 , H01L21/32137
摘要： A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.
摘要翻译：一种用于在包括具有包括图案特征的工艺表面的半导体晶片的等离子体蚀刻工艺中补偿半导体工艺晶片表面上的CD变化的方法; 执行第一等离子体蚀刻工艺，其中半导体晶片被加热到至少两个可选择性控制的温度区域; 确定相对于包括所述两个可选择性控制的温度区域的所述工艺表面的预定区域上的参考尺寸的蚀刻特征的第一尺寸变化; 确定所述两个可选择性控制的温度区域的操作温度，以实现所述第一尺寸变化中的目标尺寸变化变化以实现期望的第二维度变化; 将工艺表面等离子体蚀刻到所需的工作温度; 以及确定用于至少一个随后等离子体蚀刻工艺中的实际尺寸变化变化。

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