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1. 发明授权

US09768305B2 Gradient ternary or quaternary multiple-gate transistor 有权
公开(公告)号：US09768305B2
公开(公告)日：2017-09-19
申请号：US12616068
申请日：2009-11-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L31/0304 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7851 , H01L29/66795
摘要： An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch.

2. 发明授权

US09601328B2 Growing a III-V layer on silicon using aligned nano-scale patterns 有权
公开(公告)号：US09601328B2
公开(公告)日：2017-03-21
申请号：US12842546
申请日：2010-07-23
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/02 , H01L29/04 , H01L29/66 , H01L29/06
CPC分类号： H01L21/02546 , H01L21/02381 , H01L21/02433 , H01L21/02609 , H01L21/02639 , H01L21/76224 , H01L29/045 , H01L29/0665 , H01L29/66522
摘要： A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.

3. 发明授权

US09406518B2 (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate 有权
标题翻译：（110）表面取向，用于降低高K电介质和III-V族化合物半导体衬底之间的费米能级钉扎
公开(公告)号：US09406518B2
公开(公告)日：2016-08-02
申请号：US13299529
申请日：2011-11-18
申请人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
发明人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
IPC分类号： H01L21/28 , H01L29/51 , H01L29/66 , H01L29/04 , H01L29/20 , H01L29/78 , H01L29/45
CPC分类号： H01L29/785 , H01L21/28264 , H01L21/3081 , H01L29/045 , H01L29/0649 , H01L29/20 , H01L29/452 , H01L29/4916 , H01L29/517 , H01L29/66522
摘要： A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
摘要翻译：公开了一种具有改进的器件性能的器件及其制造方法。示例性器件包括III-V族化合物半导体衬底，其包括具有（110）结晶取向的表面和设置在III-V族化合物半导体衬底上的栅叠层。栅极堆叠包括设置在具有（110）晶体取向的表面上的高k电介质层，以及设置在高k电介质层上的栅电极。

4. 发明授权

US08841701B2 FinFET device having a channel defined in a diamond-like shape semiconductor structure 有权
标题翻译：具有限定在菱形半导体结构中的沟道的FinFET器件
公开(公告)号：US08841701B2
公开(公告)日：2014-09-23
申请号：US13220979
申请日：2011-08-30
申请人： You-Ru Lin , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： You-Ru Lin , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/66 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02609 , H01L21/30604 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/7853
摘要： The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
摘要翻译：本公开提供了一种FinFET器件。 FinFET器件包括第一半导体材料的半导体衬底; 覆盖半导体衬底的第一半导体材料的鳍结构，其中鳍结构具有第一晶面取向的顶表面; 设置在所述翅片结构的顶表面上的第二半导体材料的菱形形状结构，其中所述菱形形状结构具有至少一个第二晶面取向的表面; 设置在所述菱形形状结构上的栅极结构，其中所述栅极结构分离源极区域和漏极区域; 以及在源极和漏极区域之间以菱形形状结构限定的沟道区域。

5. 发明授权

US08836016B2 Semiconductor structures and methods with high mobility and high energy bandgap materials 有权
标题翻译：具有高迁移率和高能带隙材料的半导体结构和方法
公开(公告)号：US08836016B2
公开(公告)日：2014-09-16
申请号：US13415339
申请日：2012-03-08
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/772
CPC分类号： H01L29/7851 , H01L21/0259 , H01L21/02636 , H01L21/02639 , H01L21/02658 , H01L21/76224 , H01L21/8252 , H01L29/0649 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/267 , H01L29/66462 , H01L29/66522 , H01L29/66795 , H01L29/7786 , H01L29/7842 , H01L29/7848 , H01L29/785
摘要： An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
摘要翻译：实施例是包括基板，高能带隙材料和高载流子迁移率材料的结构。衬底包括第一隔离区域和第二隔离区域。第一隔离区域和第二隔离区域中的每一个在第一和第二隔离区域之间延伸到衬底的第一表面的下方。高能带隙材料在衬底的第一表面上方并且设置在第一和第二隔离区之间。高载流子迁移率材料超过高能带隙材料。高载流子迁移率材料比第一和第二隔离区域的相应顶表面高，以形成翅片。

6. 发明授权

US08809202B2 Methods of manufacturing semiconductor devices including use of a protective material 有权
标题翻译：制造包括使用保护材料的半导体器件的方法
公开(公告)号：US08809202B2
公开(公告)日：2014-08-19
申请号：US13396515
申请日：2012-02-14
申请人： Chih-Hui Weng , Wei-Sheng Yun , Shao-Ming Yu , Hsin-Chih Chen , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hui Weng , Wei-Sheng Yun , Shao-Ming Yu , Hsin-Chih Chen , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/31
CPC分类号： H01L21/823412 , H01L21/3083 , H01L21/32 , H01L21/823418 , H01L21/823481 , H01L25/50 , H01L29/1054 , H01L29/66651 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.
摘要翻译：公开了制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括提供工件，以及在工件的底表面和边缘上形成保护材料。加工工件的顶面。保护材料在加工工件的上表面时保护工件的边缘和底面。

7. 发明授权

US08759920B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08759920B2
公开(公告)日：2014-06-24
申请号：US13486343
申请日：2012-06-01
申请人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号： H01L21/70
CPC分类号： H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。常见的接触特征是自对准接触。

8. 发明授权

US08629478B2 Fin structure for high mobility multiple-gate transistor 有权
标题翻译：用于高迁移率多栅极晶体管的鳍结构
公开(公告)号：US08629478B2
公开(公告)日：2014-01-14
申请号：US12797839
申请日：2010-06-10
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/267 , H01L29/66795 , H01L29/7842
摘要： A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer.
摘要翻译：用于半导体晶体管的垂直翅片结构包括半导体衬底，衬底顶部的翅片层，覆盖翅片层的覆盖层，其中衬底包括IV族半导体材料，鳍层包括IV族半导体材料，封盖层包含III-V族的半导体化合物。鳍层可以包括Ge，SiGe，SiC或其任何组合。半导体衬底可以包括Si，Ge，SiGe或SiC。覆盖层可以包括GaAs，InGaAs，InAs，InSb，GaSb，GaN，InP或其任何组合。覆盖层可以提供与半导体衬底超过4％的晶格失配。翅片层可以位于提供与相邻装置隔离的浅沟槽绝缘（STI）层之间。垂直翅片结构还可以包括覆盖覆盖层的高k电介质层和覆盖高k电介质层的金属栅极层。

9. 发明授权

US08569146B2 Isolation structure for strained channel transistors 有权
标题翻译：应变通道晶体管的隔离结构
公开(公告)号：US08569146B2
公开(公告)日：2013-10-29
申请号：US13013296
申请日：2011-01-25
申请人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee , Chung-Hu Ge
发明人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee , Chung-Hu Ge
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L29/1054 , H01L29/7846 , H01L29/7848
摘要： A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
摘要翻译：公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

10. 发明申请

US20130248948A1 Source/Drain Profile for FinFET 有权
公开(公告)号：US20130248948A1
公开(公告)日：2013-09-26
申请号：US13426106
申请日：2012-03-21
申请人： Ta-Chun Ma , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Ta-Chun Ma , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02639 , H01L21/30604 , H01L21/3083 , H01L29/045 , H01L29/0688 , H01L29/1037 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7851 , H01L29/7853
摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.

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